Datasheet AD8556 (Analog Devices) - 27
| Fabricante | Analog Devices |
| Descripción | Digitally Programmable Sensor Signal Amplifier with EMI Filters |
| Páginas / Página | 27 / 27 — Data Sheet. AD8556. OUTLINE DIMENSIONS. 5.00 (0.1968) 4.80 (0.1890). 4.00 … |
| Revisión | B |
| Formato / tamaño de archivo | PDF / 701 Kb |
| Idioma del documento | Inglés |
Data Sheet. AD8556. OUTLINE DIMENSIONS. 5.00 (0.1968) 4.80 (0.1890). 4.00 (0.1574). 6.20 (0.2441). 3.80 (0.1497). 5.80 (0.2284)
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Data Sheet AD8556 OUTLINE DIMENSIONS 5.00 (0.1968) 4.80 (0.1890) 8 5 4.00 (0.1574) 6.20 (0.2441) 1 3.80 (0.1497) 5.80 (0.2284) 4 1.27 (0.0500) 0.50 (0.0196) 45° BSC 1.75 (0.0688) 0.25 (0.0099) 1.35 (0.0532) 0.25 (0.0098) 8° 0.10 (0.0040) 0° COPLANARITY 0.51 (0.0201) 1.27 (0.0500) 0.10 0.31 (0.0122) 0.25 (0.0098) SEATING 0.40 (0.0157) PLANE 0.17 (0.0067) COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. 012407-A
Figure 56. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches)
4.10 0.35 4.00 SQ 0.30 3.90 PIN 1 0.25 PIN 1 INDICATOR 13 16 INDICATOR 0.65 12 1 BSC EXPOSED 2.40 PAD 2.35 SQ 2.30 9 4 8 5 0.50 0.25 MIN TOP VIEW BOTTOM VIEW 0.40 0.30 0.80 FOR PROPER CONNECTION OF 0.75 THE EXPOSED PAD, REFER TO 0.05 MAX THE PIN CONFIGURATION AND 0.70 0.02 NOM FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COPLANARITY SEATING 0.08 PLANE 0.20 REF B 2012- 18- COMPLIANT TO JEDEC STANDARDS MO-220-WGGC-3. 07-
Figure 57. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 4 mm × 4 mm Body, Very Very Thin Quad (CP-16-20) Dimensions shown in millimeters
ORDERING GUIDE Model1 Temperature Range Package Description Package Option
AD8556ARZ −40°C to +140°C 8-Lead SOIC_N R-8 AD8556ARZ-REEL −40°C to +140°C 8-Lead SOIC_N R-8 AD8556ARZ-REEL7 −40°C to +140°C 8-Lead SOIC_N R-8 AD8556ACPZ-R2 −40°C to +140°C 16-Lead LFCSP_WQ CP-16-20 AD8556ACPZ-REEL7 −40°C to +140°C 16-Lead LFCSP_WQ CP-16-20 1 Z = RoHS Compliant Part.
©2005–2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05448-0-2/15(B)
Rev. B | Page 27 of 27 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION GAIN VALUES OPEN WIRE FAULT DETECTION SHORTED WIRE FAULT DETECTION FLOATING VPOS, VNEG, OR VCLAMP FAULT DETECTION DEVICE PROGRAMMING Digital Interface Initial State Simulation Mode Programming Mode Parity Error Detection Read Mode Sense Current Programming Procedure Determining Optimal Gain and Offset Codes EMI/RFI PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE
Figure 56. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches)
4.10 0.35 4.00 SQ 0.30 3.90 PIN 1 0.25 PIN 1 INDICATOR 13 16 INDICATOR 0.65 12 1 BSC EXPOSED 2.40 PAD 2.35 SQ 2.30 9 4 8 5 0.50 0.25 MIN TOP VIEW BOTTOM VIEW 0.40 0.30 0.80 FOR PROPER CONNECTION OF 0.75 THE EXPOSED PAD, REFER TO 0.05 MAX THE PIN CONFIGURATION AND 0.70 0.02 NOM FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COPLANARITY SEATING 0.08 PLANE 0.20 REF B 2012- 18- COMPLIANT TO JEDEC STANDARDS MO-220-WGGC-3. 07-
Figure 57. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 4 mm × 4 mm Body, Very Very Thin Quad (CP-16-20) Dimensions shown in millimeters
ORDERING GUIDE Model1 Temperature Range Package Description Package Option
AD8556ARZ −40°C to +140°C 8-Lead SOIC_N R-8 AD8556ARZ-REEL −40°C to +140°C 8-Lead SOIC_N R-8 AD8556ARZ-REEL7 −40°C to +140°C 8-Lead SOIC_N R-8 AD8556ACPZ-R2 −40°C to +140°C 16-Lead LFCSP_WQ CP-16-20 AD8556ACPZ-REEL7 −40°C to +140°C 16-Lead LFCSP_WQ CP-16-20 1 Z = RoHS Compliant Part.
©2005–2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05448-0-2/15(B)
Rev. B | Page 27 of 27 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION GAIN VALUES OPEN WIRE FAULT DETECTION SHORTED WIRE FAULT DETECTION FLOATING VPOS, VNEG, OR VCLAMP FAULT DETECTION DEVICE PROGRAMMING Digital Interface Initial State Simulation Mode Programming Mode Parity Error Detection Read Mode Sense Current Programming Procedure Determining Optimal Gain and Offset Codes EMI/RFI PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE