Datasheet AD8553 (Analog Devices) - 8

AD8553 VCC = 5V VCC = 5V GAIN = 10 GAIN = 10 N N IO IO T T A L LA PU PU PO PO
13 -016 0 4- 474 47 05 05
0 5.0 10.0 15.0 20.0 25.0 30.0 35.0 40.0 45.0 50.0 0 0.03 0.06 0.09 0.12 0.15 0.18 0.21 0.24 0.27 0.30
Figure 14. Input Offset Voltage (μV) Figure 17. Input Offset Voltage Drift (μV/°C)
VCC = 5V VCC = 5V GAIN = 1 GAIN = 1 N N IO IO T T A A L L PU PU PO PO
-015 -012 474 474 05 05
–50 –10 30 70 110 150 190 230 270 310 350 0 0.30 0.60 0.90 1.20 1.50 1.80 2.10 2.40 2.70 3.00
Figure 15. Input Offset Voltage (μV) Figure 18. Input Offset Voltage Drift (μV/°C)
VCC = 5V VCC = 5V GAIN = 100 GAIN = 100 VCM = 12.125mV VCM = 12.125mV N N IO IO T T LA LA PU PU PO PO
20 19 -0 0 4- 74 47 054 05
–250 –225 –200 –175 –150 –125 –100 –75 –50 –25 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0
Figure 16. Gain Error (m%) Figure 19. Nonlinearity (m%) Rev. A | Page 8 of 20 Document Outline FEATURES APPLICATIONS PIN CONFIGURATION GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION HIGH PSR AND CMR 1/f NOISE CORRECTION APPLICATIONS GAIN SELECTION (GAIN-SETTING RESISTORS) REFERENCE CONNECTION DISABLE FUNCTION OUTPUT FILTERING CLOCK FEEDTHROUGH LOW IMPEDANCE OUTPUT MAXIMIZING PERFORMANCE THROUGH PROPER LAYOUT POWER SUPPLY BYPASSING INPUT OVERVOLTAGE PROTECTION CAPACITIVE LOAD DRIVE CIRCUIT DIAGRAMS/CONNECTIONS OUTLINE DIMENSIONS ORDERING GUIDE