Datasheet AD8250 (Analog Devices) - 2
| Fabricante | Analog Devices |
| Descripción | 10 MHz G = 1, 2, 5, 10 iCMOS Programmable Gain Instrumentation Amplifier |
| Páginas / Página | 24 / 2 — AD8250. Data Sheet. TABLE OF CONTENTS. REVISION HISTORY. 5/13—Rev. B to … |
| Revisión | C |
| Formato / tamaño de archivo | PDF / 848 Kb |
| Idioma del documento | Inglés |
AD8250. Data Sheet. TABLE OF CONTENTS. REVISION HISTORY. 5/13—Rev. B to Rev. C. 11/10—Rev. A to Rev. B. 5/08—Rev. 0 to Rev. A
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AD8250 Data Sheet TABLE OF CONTENTS
Features .. 1 Input Bias Current Return Path ... 17 Applications ... 1 Input Protection ... 17 General Description ... 1 Reference Terminal .. 18 Functional Block Diagram .. 1 Common-Mode Input Voltage Range ... 18 Revision History ... 2 Layout .. 18 Specifications ... 3 RF Interference ... 19 Timing Diagram ... 5 Driving an ADC ... 19 Absolute Maximum Ratings .. 6 Applications ... 20 Maximum Power Dissipation ... 6 Differential Output .. 20 ESD Caution .. 6 Setting Gains with a Microcontrol er .. 20 Pin Configuration and Function Descriptions ... 7 Data Acquisition ... 21 Typical Performance Characteristics ... 8 Outline Dimensions ... 22 Theory of Operation .. 15 Ordering Guide .. 22 Gain Selection ... 15 Power Supply Regulation and Bypassing .. 17
REVISION HISTORY 5/13—Rev. B to Rev. C
Changes to Table 3 ... 6 Added Figure 17; Renumbered Sequentially ... 9 Changed 49.9 Ω to 100 Ω in Driving an ADC Section and Changes to Figure 23 .. 10 Figure 55 .. 19 Changes to Figure 24 to Figure 26 .. 11 Added Figure 29 ... 11
11/10—Rev. A to Rev. B
Changes to Figure 31 .. 12 Changes to Voltage Offset, Offset RTI V Deleted Figure 43 to Figure 46; Renumbered Sequential y .. 14 OS, Average Temperature Coefficient Parameter in Table 2 ... 3 Inserted Figure 45 and Figure 46 .. 14 Updated Outline Dimensions ... 22 Changes to Timing for Latched Gain Mode Section ... 16 Changes to Layout Section and Coupling Noise Section .. 18
5/08—Rev. 0 to Rev. A
Changes to Figure 59 .. 21 Changes to Table 1 .. 1
1/07—Revision 0: Initial Version
Changes to Table 2 .. 3 Rev. C | Page 2 of 24 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Timing Diagram Absolute Maximum Ratings Maximum Power Dissipation ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Gain Selection Transparent Gain Mode Latched Gain Mode Timing for Latched Gain Mode Power Supply Regulation and Bypassing Input Bias Current Return Path Input Protection Reference Terminal Common-Mode Input Voltage Range Layout Grounding Coupling Noise Common-Mode Rejection RF Interference Driving an ADC Applications Differential Output Setting Gains with a Microcontroller Data Acquisition Outline Dimensions Ordering Guide
AD8250 Data Sheet TABLE OF CONTENTS
Features .. 1 Input Bias Current Return Path ... 17 Applications ... 1 Input Protection ... 17 General Description ... 1 Reference Terminal .. 18 Functional Block Diagram .. 1 Common-Mode Input Voltage Range ... 18 Revision History ... 2 Layout .. 18 Specifications ... 3 RF Interference ... 19 Timing Diagram ... 5 Driving an ADC ... 19 Absolute Maximum Ratings .. 6 Applications ... 20 Maximum Power Dissipation ... 6 Differential Output .. 20 ESD Caution .. 6 Setting Gains with a Microcontrol er .. 20 Pin Configuration and Function Descriptions ... 7 Data Acquisition ... 21 Typical Performance Characteristics ... 8 Outline Dimensions ... 22 Theory of Operation .. 15 Ordering Guide .. 22 Gain Selection ... 15 Power Supply Regulation and Bypassing .. 17
REVISION HISTORY 5/13—Rev. B to Rev. C
Changes to Table 3 ... 6 Added Figure 17; Renumbered Sequentially ... 9 Changed 49.9 Ω to 100 Ω in Driving an ADC Section and Changes to Figure 23 .. 10 Figure 55 .. 19 Changes to Figure 24 to Figure 26 .. 11 Added Figure 29 ... 11
11/10—Rev. A to Rev. B
Changes to Figure 31 .. 12 Changes to Voltage Offset, Offset RTI V Deleted Figure 43 to Figure 46; Renumbered Sequential y .. 14 OS, Average Temperature Coefficient Parameter in Table 2 ... 3 Inserted Figure 45 and Figure 46 .. 14 Updated Outline Dimensions ... 22 Changes to Timing for Latched Gain Mode Section ... 16 Changes to Layout Section and Coupling Noise Section .. 18
5/08—Rev. 0 to Rev. A
Changes to Figure 59 .. 21 Changes to Table 1 .. 1
1/07—Revision 0: Initial Version
Changes to Table 2 .. 3 Rev. C | Page 2 of 24 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Timing Diagram Absolute Maximum Ratings Maximum Power Dissipation ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Gain Selection Transparent Gain Mode Latched Gain Mode Timing for Latched Gain Mode Power Supply Regulation and Bypassing Input Bias Current Return Path Input Protection Reference Terminal Common-Mode Input Voltage Range Layout Grounding Coupling Noise Common-Mode Rejection RF Interference Driving an ADC Applications Differential Output Setting Gains with a Microcontroller Data Acquisition Outline Dimensions Ordering Guide