Datasheet AD8251 (Analog Devices) - 10

AD8251 20 15 A) n ( NT 15 10 URRE C I T B+ E 10 5 S F V) F O (µV/ 5 R 0 R AND I M T B– C N ∆ 0 –5 RRE I CU OS AS –5 –10
19
BI
22 0 0 7- 7-
UT
628 628
–10
0
–15
0
INP –60 –40 –20 0 20 40 60 80 100 120 140 –50 –30 –10 10 30 50 70 90 110 130 TEMPERATURE (ºC) TEMPERATURE (°C)
Figure 18. Input Bias Current and Offset Current vs. Temperature Figure 21. ΔCMRR vs. Temperature, G = 1
140 25 G = 4 VS = ±15V G = 8 VIN = 200mV p-p 20 G = 8 RL = 2kΩ 120 15 G = 4 100 B) G = 2 ) d B 10 d R ( ( G = 2 R IN CM 5 80 GA G = 1 G = 1 0 60 –5
20 3 0 02 7- 7- 628 28
40
0
–10
06
10 100 1k 10k 100k 1M 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) FREQUENCY (Hz)
Figure 19. CMRR vs. Frequency Figure 22. Gain vs. Frequency
140 40 30 ) 120 IV /D 20 m G = 8 p 10p 100 10 ( B) d G = 4 Y T R ( 0 R G = 2 ARI E CM 80 G = 1 IN –10 NL NO –20 IN 60 A G
21
–30
24 0 0 7- 7- 28 628
40
0
–40
06
10 100 1k 10k 100k 1M –10 –8 –6 –4 –2 0 2 4 6 8 10 FREQUENCY (Hz) OUTPUT VOLTAGE (V)
Figure 20. CMRR vs. Frequency, 1 kΩ Source Imbalance Figure 23. Gain Nonlinearity vs. Output Voltage, G = 1, RL = 10 kΩ, 2 kΩ, 600 Ω Rev. B | Page 10 of 24 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING DIAGRAM ABSOLUTE MAXIMUM RATINGS MAXIMUM POWER DISSIPATION ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION GAIN SELECTION Transparent Gain Mode Latched Gain Mode Timing for Latched Gain Mode POWER SUPPLY REGULATION AND BYPASSING INPUT BIAS CURRENT RETURN PATH INPUT PROTECTION REFERENCE TERMINAL COMMON-MODE INPUT VOLTAGE RANGE LAYOUT Grounding Coupling Noise Common-Mode Rejection RF INTERFERENCE DRIVING AN ADC APPLICATIONS DIFFERENTIAL OUTPUT SETTING GAINS WITH A MICROCONTROLLER DATA ACQUISITION OUTLINE DIMENSIONS ORDERING GUIDE