Datasheet AD8253 (Analog Devices) - 3
| Fabricante | Analog Devices |
| Descripción | 10 MHz, G = 1, 10, 100, 1000 iCMOS Programmable Gain Instrumentation Amplifier |
| Páginas / Página | 24 / 3 — Data Sheet. AD8253. SPECIFICATIONS. Table 2. Parameter. Conditions. Min. … |
| Revisión | B |
| Formato / tamaño de archivo | PDF / 426 Kb |
| Idioma del documento | Inglés |
Data Sheet. AD8253. SPECIFICATIONS. Table 2. Parameter. Conditions. Min. Typ. Max. Unit
Línea de modelo para esta hoja de datos
Versión de texto del documento
link to page 5 link to page 5
Data Sheet AD8253 SPECIFICATIONS
+VS = +15 V, −VS = −15 V, VREF = 0 V @ TA = 25°C, G = 1, RL = 2 kΩ, unless otherwise noted.
Table 2. Parameter Conditions Min Typ Max Unit
COMMON-MODE REJECTION RATIO (CMRR) CMRR to 60 Hz with 1 kΩ Source Imbalance +IN = −IN = −10 V to +10 V G = 1 80 100 dB G = 10 96 120 dB G = 100 100 120 dB G = 1000 100 120 dB CMRR to 20 kHz1 +IN = −IN = −10 V to +10 V G = 1 80 dB G = 10 96 dB G = 100 100 dB G = 1000 100 dB NOISE Voltage Noise, 1 kHz, RTI G = 1 45 nV/√Hz G = 10 12 nV/√Hz G = 100 11 nV/√Hz G = 1000 10 nV/√Hz 0.1 Hz to 10 Hz, RTI G = 1 2.5 μV p-p G = 10 1 μV p-p G = 100 0.5 μV p-p G = 1000 0.5 μV p-p Current Noise, 1 kHz 5 pA/√Hz Current Noise, 0.1 Hz to 10 Hz 60 pA p-p VOLTAGE OFFSET Offset RTI VOS G = 1, 10, 100, 1000 ±150 + 900/G μV Over Temperature T = −40°C to +85°C ±210 + 900/G μV Average TC T = −40°C to +85°C ±1.2 + 5/G μV/°C Offset Referred to the Input vs. Supply (PSR) VS = ±5 V to ±15 V ±5 + 25/G μV/V INPUT CURRENT Input Bias Current 5 50 nA Over Temperature2 T = −40°C to +85°C 40 60 nA Average TC T = −40°C to +85°C 400 pA/°C Input Offset Current 5 40 nA Over Temperature T = −40°C to +85°C 40 nA Average TC T = −40°C to +85°C 160 pA/°C DYNAMIC RESPONSE Small-Signal −3 dB Bandwidth G = 1 10 MHz G = 10 4 MHz G = 100 550 kHz G = 1000 60 kHz Settling Time 0.01% ΔOUT = 10 V step G = 1 700 ns G = 10 680 ns G = 100 1.5 μs G = 1000 14 μs Rev. B | Page 3 of 24 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING DIAGRAM ABSOLUTE MAXIMUM RATINGS MAXIMUM POWER DISSIPATION ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION GAIN SELECTION Transparent Gain Mode Latched Gain Mode Timing for Latched Gain Mode POWER SUPPLY REGULATION AND BYPASSING INPUT BIAS CURRENT RETURN PATH INPUT PROTECTION REFERENCE TERMINAL COMMON-MODE INPUT VOLTAGE RANGE LAYOUT Grounding Coupling Noise Common-Mode Rejection RF INTERFERENCE DRIVING AN ANALOG-TO-DIGITAL CONVERTER APPLICATIONS INFORMATION DIFFERENTIAL OUTPUT SETTING GAINS WITH A MICROCONTROLLER DATA ACQUISITION OUTLINE DIMENSIONS ORDERING GUIDE
Data Sheet AD8253 SPECIFICATIONS
+VS = +15 V, −VS = −15 V, VREF = 0 V @ TA = 25°C, G = 1, RL = 2 kΩ, unless otherwise noted.
Table 2. Parameter Conditions Min Typ Max Unit
COMMON-MODE REJECTION RATIO (CMRR) CMRR to 60 Hz with 1 kΩ Source Imbalance +IN = −IN = −10 V to +10 V G = 1 80 100 dB G = 10 96 120 dB G = 100 100 120 dB G = 1000 100 120 dB CMRR to 20 kHz1 +IN = −IN = −10 V to +10 V G = 1 80 dB G = 10 96 dB G = 100 100 dB G = 1000 100 dB NOISE Voltage Noise, 1 kHz, RTI G = 1 45 nV/√Hz G = 10 12 nV/√Hz G = 100 11 nV/√Hz G = 1000 10 nV/√Hz 0.1 Hz to 10 Hz, RTI G = 1 2.5 μV p-p G = 10 1 μV p-p G = 100 0.5 μV p-p G = 1000 0.5 μV p-p Current Noise, 1 kHz 5 pA/√Hz Current Noise, 0.1 Hz to 10 Hz 60 pA p-p VOLTAGE OFFSET Offset RTI VOS G = 1, 10, 100, 1000 ±150 + 900/G μV Over Temperature T = −40°C to +85°C ±210 + 900/G μV Average TC T = −40°C to +85°C ±1.2 + 5/G μV/°C Offset Referred to the Input vs. Supply (PSR) VS = ±5 V to ±15 V ±5 + 25/G μV/V INPUT CURRENT Input Bias Current 5 50 nA Over Temperature2 T = −40°C to +85°C 40 60 nA Average TC T = −40°C to +85°C 400 pA/°C Input Offset Current 5 40 nA Over Temperature T = −40°C to +85°C 40 nA Average TC T = −40°C to +85°C 160 pA/°C DYNAMIC RESPONSE Small-Signal −3 dB Bandwidth G = 1 10 MHz G = 10 4 MHz G = 100 550 kHz G = 1000 60 kHz Settling Time 0.01% ΔOUT = 10 V step G = 1 700 ns G = 10 680 ns G = 100 1.5 μs G = 1000 14 μs Rev. B | Page 3 of 24 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING DIAGRAM ABSOLUTE MAXIMUM RATINGS MAXIMUM POWER DISSIPATION ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION GAIN SELECTION Transparent Gain Mode Latched Gain Mode Timing for Latched Gain Mode POWER SUPPLY REGULATION AND BYPASSING INPUT BIAS CURRENT RETURN PATH INPUT PROTECTION REFERENCE TERMINAL COMMON-MODE INPUT VOLTAGE RANGE LAYOUT Grounding Coupling Noise Common-Mode Rejection RF INTERFERENCE DRIVING AN ANALOG-TO-DIGITAL CONVERTER APPLICATIONS INFORMATION DIFFERENTIAL OUTPUT SETTING GAINS WITH A MICROCONTROLLER DATA ACQUISITION OUTLINE DIMENSIONS ORDERING GUIDE