Datasheet PE43610 (pSemi) - 3

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PE43610 UltraCMOS® RF Digital Step Attenuator Recommended Operating Conditions Table 2
lists the recommending operating condition for the PE43610. Devices should not be operated outside the recommended operating conditions listed below.
Table 2 • Recommended Operating Condition for the PE43610 Parameter Min Typ Max Unit Normal mode, VSS_EXT = 0V(1)
Positive supply voltage, VDD 2.3 3.3 5.5 V Positive supply current, I
(3)
DD 170 260 µA
Bypass mode, VSS_EXT = –3.0V(2)
Positive supply voltage, VDD (VDD ≥ 3.4V. See
Table 3
for ful spec 3.1 3.4 5.5 V compliance.) Positive supply current, I
(3)
DD 125 170 µA Negative supply voltage, VSS_EXT –3.3 –3.0 –2.7 V Negative supply current, ISS -40 -16 µA
Normal or bypass mode
Digital input high 1.17 3.60 V Digital input low –0.3 0.6 V Digital input current
(4)
10 20 µA RF input power, CW
(5) (7)
28 dBm RF input power, pulsed
(6) (7)
31 dBm Operating temperature range –40 +25 +105 °C
Notes:
1) Normal mode: Connect VSS_EXT (pin 2) to GND (VSS_EXT = 0V) to enable internal negative voltage generator. 2) Bypass mode: Use VSS_EXT (pin 2) to bypass and disable internal negative voltage generator. 3) Due to startup inrush current, a minimum current limit of 600 µA is al owed for normal operation of the DSA. 4) Applies to al pins except pins 18, 22, 23 and 24. P/S (pin 18), A0/D4 (pin 22), A1/D5 (pin 23), and A2/D6 (pin 24) have internal 1.5 MΩ pul -up resistor to internal 1.8V VDD. 5) 100% duty cycle, al bands, 50Ω. 6) ≤ 5% duty cycle, 50Ω. 7) The maximum peak envelope of any OFDM complex waveform signal, such as CP-OFDM, should not exceed the maximum peak RF input power in
Table 1
. The maximum average power of any complex waveform should not exceed the operating maximum RF input power, CW. DOC-93588-3 – (06/2020) Page 3 of 21 www.psemi.com Document Outline Features Applications Product Description Optional External VSS Control Absolute Maximum Ratings ESD Precautions Latch-up Immunity Recommended Operating Conditions Electrical Specifications Switching Frequency Spur-free Performance Glitch-safe Attenuation State The PE43610 features a novel architecture to provide safe transition behavior when changing attenuation states. When RF input power is applied, positive output power spikes are prevented during attenuation state changes by optimized internal timing c... Truth Tables Serial Addressable Register Map Programming Options Parallel/Serial Selection Parallel Mode Interface For direct parallel programming, the LE line should be pulled HIGH. Changing attenuation state control values changes the device state to new attenuation. Direct mode is ideal for manual control of the device (using hardwire, switches, or jumpers). Serial-Addressable Interface Power-up Control Settings Typical Performance Data Pin Configuration Packaging Information Moisture Sensitivity Level Package Drawing Top-Marking Specification Tape and Reel Specification Ordering Information