Datasheet XDPL8219 (Infineon) - 10

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XDPL8219 Digital Flyback Controller IC XDP™ Digital Power 3 Functional description On-time limits
The on-time limits in
Figure 4
are adaptive based on the estimated input voltage Vin. • QRMn/DCM: To sense the output over-voltage level of VoutOV parameter, the device calculates a ton,min,V,out,sense(Vin) variable, which is the estimated minimum on-time to achieve the desired minimum transformer demagnetization time of tmin,demag parameter, at the peak of the estimated input voltage Vin,peak. The minimum on-time limit ton,min(Vin) is based on the ton,min parameter or the ton,min,V,out,sense(Vin) variable, whichever is higher, as shown in
Figure 7
. For Vin between the lowest operational input voltage parameter Vin,low and the input over-voltage protection level parameter VinOV, the maximum on-time limit ton,max(Vin) is scaled to compensate the influence of input voltage on feedback gain. For Vin from Vin,low to the input under-voltage protection level parameter Vin,UV, ton,max(Vin) can be linearly reduced from ton,max,at,V,in,low parameter to ton,max,at, Vin,UV parameter, to limit the maximum power during brown-out. • ABM: For Vin decreased from Vin,high, the ABM minimum on-time limit ton,min,ABM(Vin) is increased from ton,min,ABM parameter, to reduce the burst pulse number for a lower standby power at lower input voltage. ton,max(Vin) ton,min(Vin) ton,min,V,out,sense(Vin) ton,min,ABM(Vin) ton,max,at,V,in,low Nvalley =1 ton,max,at,V,in,UV Nvalley = Nvalley,min,at,V,in,high (E.g. Using 4 as example) ton,min ton,min,ABM V V V inUV Vin,low in,high VinOV in
Figure 7 On-time limits adaptation based on estimated input voltage Vin
Note: ton,min(Vin), ton,max(Vin), and ton,min,ABM(Vin) are adapted once in every
Operation cycle
.
Feedback voltage maximum limit
When the regulated mode is entered, the filtered feedback voltage maximum limit VFB,filtered,max is ramped up from VFB,limit,start (1.2 V typ.) to VREF (2.428 V typ.), with an incremental voltage step of VFB,limit,step parameter after every tFB,limit,step. As shown in
Figure 8
, when VFB,filtered is higher than VFB,filtered,max initially in the regulated mode entering, the feedback voltage mapping is based on VFB,filtered,max ramp, to prevent the excessive output voltage overshoot during output rise. When VFB,filtered gets lower than VFB,filtered,max, the feedback voltage mapping then follows VFB,filtered, for the steady-state output regulation. Data Sheet 10 Revision 1.1 2020-08-26 Document Outline Features Product validation Potential applications Description Table of contents 1 Pin configuration 2 Functional block diagram 3 Functional description 3.1 Startup 3.2 Regulated mode 3.3 Operation cycle 3.4 Line synchronization 3.5 Enhanced power quality 3.6 Switching frequency dithering for constant DC input voltage 3.7 Configurable gate voltage rising slope at GD pin 3.8 UART reporting 3.9 Input voltage and output voltage estimation 3.9.1 Output voltage estimation 3.9.2 Input voltage estimation 3.10 Protection features 3.10.1 Primary MOSFET overcurrent protection 3.10.2 Output undervoltage protection 3.10.3 Output overvoltage protection 3.10.4 Transformer demagnetization time shortage protection 3.10.5 Minimum input voltage startup check and input undervoltage protection 3.10.6 Maximum input voltage startup check and input overvoltage protection 3.10.7 VCC undervoltage lockout 3.10.8 VCC undervoltage protection 3.10.9 VCC overvoltage protection 3.10.10 IC overtemperature protection 3.10.11 Other protections 3.10.12 Protection reactions 3.11 Debug mode 4 List of Parameters 5 Electrical Characteristics and Parameters 5.1 Package Characteristics 5.2 Absolute Maximum Ratings 5.3 Operating Conditions 5.4 DC Electrical characteristics 6 Package Dimensions 7 References 8 Revision History Glossary ABM ADC BOM CCM CRC CV DCM EMI FB GUI HID IC IIR OCP1 OTP PCB PC PFC PF PWM QRM1 QRMn RAM SSR THD UART USB UVLO Disclaimer