Datasheet XDPL8219 (Infineon) - 9

FabricanteInfineon
DescripciónDigital Flyback Controller IC
Páginas / Página45 / 9 — XDPL8219 Digital Flyback Controller IC. XDP™ Digital Power. 3 Functional …
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XDPL8219 Digital Flyback Controller IC. XDP™ Digital Power. 3 Functional description. Figure 5. Typical ABM switching waveforms

XDPL8219 Digital Flyback Controller IC XDP™ Digital Power 3 Functional description Figure 5 Typical ABM switching waveforms

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XDPL8219 Digital Flyback Controller IC XDP™ Digital Power 3 Functional description
VFB VFB,filtered ton = α nABM = 4 ton = β ton = β nABM = 3 nABM = 3 wake wake wake sleep up up sleep up sleep T≈1/f t burst T≈1/fburst VGD 1/fsw,min 1/fsw,min 1/fsw,min ton = α ton = β nABM = 4 nABM = 3 t Approx. Approx. Approx. nwakeup nwakeup nwakeup x 19 µs x 19 µs x 19 µs
Figure 5 Typical ABM switching waveforms
Note: The ABM switching pulse frequency typically follows the minimum switching frequency parameter fsw,min (26.9 kHz typ.) but it can be modulated over every
Operation cycle
to achieve the
Switching frequency dithering for constant DC input voltage
.
Regualted mode CS pin maximum voltage and minimum valley number limits
In regulated mode, the minimum valley number limit Nvalley,min(Vin) and CS pin maximum voltage limit VOCP1(Vin) are both adaptive based on the estimated input voltage Vin, as shown in
Figure 6
, to prevent excessive output power at higher input voltage. The effective on-time is lower than the mapped ton in
Figure 4
, if the conducting MOSFET current rises to a level of VOCP1(Vin) after the CS leading edge blanking time tCS,LEB (480 ns typ.). VOCP1(Vin) Nvalley,min(Vin) VOCP1,at,V,in,low VOCP1,at,V,in,high Nvalley,min,at,V,in,high 1 Vin,low Vin,high Vin
Figure 6 Regulated mode CS pin maximum voltage and minimum valley number limits adaptation based on estimated input voltage Vin
Note: VOCP1(Vin) and Nvalley,min(Vin) are adapted once in every
Operation cycle
. Data Sheet 9 Revision 1.1 2020-08-26 Document Outline Features Product validation Potential applications Description Table of contents 1 Pin configuration 2 Functional block diagram 3 Functional description 3.1 Startup 3.2 Regulated mode 3.3 Operation cycle 3.4 Line synchronization 3.5 Enhanced power quality 3.6 Switching frequency dithering for constant DC input voltage 3.7 Configurable gate voltage rising slope at GD pin 3.8 UART reporting 3.9 Input voltage and output voltage estimation 3.9.1 Output voltage estimation 3.9.2 Input voltage estimation 3.10 Protection features 3.10.1 Primary MOSFET overcurrent protection 3.10.2 Output undervoltage protection 3.10.3 Output overvoltage protection 3.10.4 Transformer demagnetization time shortage protection 3.10.5 Minimum input voltage startup check and input undervoltage protection 3.10.6 Maximum input voltage startup check and input overvoltage protection 3.10.7 VCC undervoltage lockout 3.10.8 VCC undervoltage protection 3.10.9 VCC overvoltage protection 3.10.10 IC overtemperature protection 3.10.11 Other protections 3.10.12 Protection reactions 3.11 Debug mode 4 List of Parameters 5 Electrical Characteristics and Parameters 5.1 Package Characteristics 5.2 Absolute Maximum Ratings 5.3 Operating Conditions 5.4 DC Electrical characteristics 6 Package Dimensions 7 References 8 Revision History Glossary ABM ADC BOM CCM CRC CV DCM EMI FB GUI HID IC IIR OCP1 OTP PCB PC PFC PF PWM QRM1 QRMn RAM SSR THD UART USB UVLO Disclaimer