Datasheet XDPL8219 (Infineon) - 8

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XDPL8219 Digital Flyback Controller IC XDP™ Digital Power 3 Functional description Filtered feedback voltage mapping Figure 4 Filtered feedback voltage mapping
• QRMn/DCM: The ton, tsw,min and Nvalley in
Figure 4
are mapped from the filtered feedback voltage VFB,filtered. In QRMn, to switch on the MOSFET at the Nvalley of the drain voltage, the system-dependent QRMn switching period tsw,QRMn has to be more than tsw,min. If the drain voltage valley of Nvalley happens before tsw,min is reached, the controller operates in DCM and the DCM switching period tsw,DCM follows tsw,min. For a smoother transition when the Nvalley changes, the device can compensate the ton curve using cvalley,comp parameter. To stabilize the Nvalley in steady state operation, a hysteresis on Nvalley change is applied, and the Nvalley is only updated once in each
Operation cycle
. If the Nvalley change is more than a Nvalley,fast parameter, the controller can speed up the Nvalley update for a better dynamic load response. Note: Either ton or tsw,min, or both can be modulated over every
Operation cycle
to achieve either the
Enhanced power quality
for AC input, or the
Switching frequency dithering for constant DC input voltage
. • ABM: ton and nburst are mapped from VFB,filtered taken at the last pulse of previous burst cycle. Typically, the controller has a burst interval which is approximately the configured 1/fburst and enters the sleep mode for power saving after completing the last pulse of each burst cycle, as shown in
Figure 5
. However, if the UART reporting feature is enabled with ENUART,reporting parameter, either a longer than typical burst interval or a delayed sleep mode entry, or both can occur occasionally, for instance when the UART signal transmission can not be completed within the typical burst interval or before the last pulse of a burst cycle. Data Sheet 8 Revision 1.1 2020-08-26 Document Outline Features Product validation Potential applications Description Table of contents 1 Pin configuration 2 Functional block diagram 3 Functional description 3.1 Startup 3.2 Regulated mode 3.3 Operation cycle 3.4 Line synchronization 3.5 Enhanced power quality 3.6 Switching frequency dithering for constant DC input voltage 3.7 Configurable gate voltage rising slope at GD pin 3.8 UART reporting 3.9 Input voltage and output voltage estimation 3.9.1 Output voltage estimation 3.9.2 Input voltage estimation 3.10 Protection features 3.10.1 Primary MOSFET overcurrent protection 3.10.2 Output undervoltage protection 3.10.3 Output overvoltage protection 3.10.4 Transformer demagnetization time shortage protection 3.10.5 Minimum input voltage startup check and input undervoltage protection 3.10.6 Maximum input voltage startup check and input overvoltage protection 3.10.7 VCC undervoltage lockout 3.10.8 VCC undervoltage protection 3.10.9 VCC overvoltage protection 3.10.10 IC overtemperature protection 3.10.11 Other protections 3.10.12 Protection reactions 3.11 Debug mode 4 List of Parameters 5 Electrical Characteristics and Parameters 5.1 Package Characteristics 5.2 Absolute Maximum Ratings 5.3 Operating Conditions 5.4 DC Electrical characteristics 6 Package Dimensions 7 References 8 Revision History Glossary ABM ADC BOM CCM CRC CV DCM EMI FB GUI HID IC IIR OCP1 OTP PCB PC PFC PF PWM QRM1 QRMn RAM SSR THD UART USB UVLO Disclaimer