Datasheet LT3021, LT3021-1.2, LT3021-1.5, LT3021-1.8 (Analog Devices) - 10

LT3021/LT3021-1.2/ LT3021-1.5/LT3021-1.8
PIN FUNCTIONS (DH Package/S8 Package) OUT (Pins 3, 4/Pin 2):
These pins supply power to the load. drain logic, normally several microamperes, and the SHDN Use a minimum output capacitor of 3.3µF to prevent oscil- pin current, typically 2.5µA. If unused, connect the SHDN lations. Applications with large load transients require larger pin to VIN. The LT3021 does not function if the SHDN pin output capacitors to limit peak voltage transients. See the is not connected. Applications Information section for more information on
IN (Pins 12, 14/Pin 8):
These pins supply power to the output capacitance and reverse output characteristics. device. The LT3021 requires a bypass capacitor at IN if
SENSE (Pin 7/Pin 3, Fixed Voltage Device Only):
This pin it is more than six inches away from the main input filter is the sense point for the internal resistor divider. It should capacitor. The output impedance of a battery rises with be tied directly to the OUT pins for best results. frequency, so include a bypass capacitor in battery-pow-
ADJ (Pin 7/Pin 3):
This pin is the inverting terminal to the ered circuits. A bypass capacitor in the range of 3.3µF to error amplifier. Its typical input bias current of 20nA flows 10µF suffices. The LT3021 withstands reverse voltages out of the pin (see curve of ADJ Pin Bias Current vs Tem- on the IN pin with respect to ground and the OUT pin. In perature in the Typical Performance Characteristics). The the case of a reversed input, which occurs if a battery is ADJ pin reference voltage is 200mV (referred to GND). plugged in backwards, the LT3021 acts as if a diode is in series with its input. No reverse current flows into the
AGND (Pin 8/Pin 4):
Ground. LT3021 and no reverse voltage appears at the load. The
PGND (Pins 10, 17/Pin 6):
Ground. device protects itself and the load.
SHDN (Pin 9/Pin 5):
The SHDN pin puts the LT3021 into
EXPOSED PAD (Pin 17, DH16 Package Only):
Ground. a low power state. Pulling the SHDN pin low turns the Solder Pin 17 to the PCB ground. Connect directly to Pins output off. Drive the SHDN pin with either logic or an open 8, 10 for best performance. collector/drain device with a pull-up resistor. The pull-up
NC (Pins 1, 2, 5, 6, 11, 13, 15, 16/Pins 1, 7):
No Connect. resistor supplies the pull-up current to the open collector/ No connect pins may be floated, tied to IN or tied to GND.
BLOCK DIAGRAM (DH Package/S8 Package)
IN (12, 14/8) SHDN R3 SHUTDOWN THERMAL (9/5) SHUTDOWN D1 – Q3 CURRENT ERROR AMP Q1 + GAIN 200mV BIAS CURRENT AND D2 OUT REFERENCE (3,4/2) GENERATOR 212mV – OUT SENSE (7/3) NO-LOAD Q2 RECOVERY + R2 ADJ 25k (7/3) R1
FIXED
NOTE:
VOUT R1 R2
FOR LT3021 ADJUST PIN (7/3) IS CONNECTED TO THE ADJUST PIN, R1 AND R2 ARE EXTERNAL. 1.2V 20k 100k GND FOR LT3021-1.X PIN (7/3) IS CONNECTED TO THE 1.5V 20k 130k (8,10,17/4,6) 1.8V 20k 160k 3021 BD OUTPUT SENSE PIN, R1 AND R2 ARE INTERNAL. Rev.D 10 For more information www.analog.com Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Typical Performance Characteristics Pin Functions Applications Information Package Description