Datasheet ADP122, ADP123 (Analog Devices) - 5

Data Sheet ADP122/ADP123 ABSOLUTE MAXIMUM RATINGS Table 3.
application and board layout. In applications in which high maxi-
Parameter Rating
mum power dissipation exists, close attention to thermal board design is required. The value of θ VIN to GND −0.3 V to +6.5 V JA may vary, depending on PCB material, layout, and environmental conditions. The specified ADJ to GND −0.3 V to +6.5 V values of θ EN to GND −0.3 V to +6.5 V JA are based on a 4-layer, 4 inch × 3 inch circuit board. Refer to JESD51-7 for detailed information on the board VOUT to GND −0.3 V to VIN construction Storage Temperature Range −65°C to +150°C Operating Ambient Temperature Range −40°C to +125°C ΨJB is the junction-to-board thermal characterization parameter Operating Junction Temperature −40°C to +125°C and is measured in °C/W. The ΨJB of the package is based on Soldering Conditions JEDEC J-STD-020 modeling and calculation using a 4-layer board. The Guidelines for Reporting and Using Package Thermal Information: JESD51-12 Stresses above those listed under Absolute Maximum Ratings may states that thermal characterization parameters are not the same cause permanent damage to the device. This is a stress rating as thermal resistances. ΨJB measures the component power flowing only; functional operation of the device at these or any other through multiple thermal paths rather than a single path as in conditions above those indicated in the operational section of thermal resistance, θJB. Therefore, ΨJB thermal paths include this specification is not implied. Exposure to absolute maximum convection from the top of the package as wel as radiation from rating conditions for extended periods may affect device reliability. the package—factors that make ΨJB more useful in real-world applications. Maximum junction temperature (T
THERMAL DATA
J) is calculated from the board temperature (TB) and power dissipation (PD) Absolute maximum ratings apply individually only, not in using the formula combination. The ADP122/ADP123 can be damaged when the TJ = TB + (PD × ΨJB) junction temperature limits are exceeded. Monitoring ambient temperature does not guarantee that T Refer to JESD51-8 and JESD51-12 for more detailed information J will remain within the specified temperature limits. In applications with high power about ΨJB. dissipation and poor thermal resistance, the maximum ambient
THERMAL RESISTANCE
temperature may have to be derated. θJA and ΨJB are specified for the worst-case conditions, that is, a In applications with moderate power dissipation and low PCB device soldered in a circuit board for surface-mount packages. thermal resistance, the maximum ambient temperature can exceed the maximum limit as long as the junction temperature
Table 4. Thermal Resistance
is within specification limits. The junction temperature (T
Package Type θ Ψ Unit JA JB
J) of the device is dependent on the ambient temperature (T 5-Lead TSOT 170 43 °C/W A), the power dissipation of the device (P 6-Lead 2 mm × 2 mm LFCSP 68.9 44.1 °C/W D), and the junction-to-ambient thermal resistance of the package (θ JA). Maximum junction temperature (T
ESD CAUTION
J) is calculated from the ambient temperature (TA) and power dissipation (PD) using the formula TJ = TA + (PD × θJA) The junction-to-ambient thermal resistance (θ JA) of the package is based on modeling and calculation using a 4-layer board. The junction-to-ambient thermal resistance is highly dependent on the Rev. E | Page 5 of 24 Document Outline Features Applications General Description Typical Application Circuits Revision History Specifications Recommended Specifications Absolute Maximum Ratings Thermal Data Thermal Resistance ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Theory of Operation Applications Information Capacitor Selection Output Capacitor Input Bypass Capacitor Input and Output Capacitor Properties Undervoltage Lockout Enable Feature Current Limit and Thermal Overload Protection Thermal Considerations Junction Temperature Calculations For TSOT Package Junction Temperature Calculations For LFCSP Package Printed Circuit Board Layout Considerations Outline Dimensions Ordering Guide