Datasheet ADP150 (Analog Devices) - 3

FabricanteAnalog Devices
DescripciónUltralow Noise, 150 mA CMOS Linear Regulator
Páginas / Página20 / 3 — Data Sheet. ADP150. SPECIFICATIONS. Table 1. Parameter. Symbol. Test …
RevisiónC
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Data Sheet. ADP150. SPECIFICATIONS. Table 1. Parameter. Symbol. Test Conditions/Comments. Min. Typ. Max. Unit

Data Sheet ADP150 SPECIFICATIONS Table 1 Parameter Symbol Test Conditions/Comments Min Typ Max Unit

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Data Sheet ADP150 SPECIFICATIONS
VIN = (VOUT + 0.4 V) or 2.2 V, whichever is greater; EN = VIN, IOUT = 10 mA, CIN = COUT = 1 µF, TA = 25°C, unless otherwise noted.
Table 1. Parameter Symbol Test Conditions/Comments Min Typ Max Unit
INPUT VOLTAGE RANGE V T = −40°C to +125°C 2.2 5.5 V IN J OPERATING SUPPLY CURRENT I I = 0 µA 10 µA GND OUT I = 0 µA, T = −40°C to +125°C 22 µA OUT J I = 100 µA 20 µA OUT I = 100 µA, T = −40°C to +125°C 40 µA OUT J I = 10 mA 60 µA OUT I = 10 mA, T = −40°C to +125°C 100 µA OUT J I = 150 mA 220 µA OUT I = 150 mA, T = −40°C to +125°C 320 µA OUT J SHUTDOWN CURRENT I EN = GND 0.2 µA GND-SD EN = GND, T = −40°C to +125°C 1.0 µA J OUTPUT VOLTAGE ACCURACY 5-Lead TSOT V I = 10 mA −1 +1 % OUT OUT 100 µA < I < 150 mA, V = (V + 0.4 V) to 5.5 V, −2.5 +1.5 % OUT IN OUT T = −40°C to +125°C J 4-Ball WLCSP V I = 10 mA −1 +1 % OUT OUT 100 µA < I < 150 mA, V = (V + 0.4 V) to 5.5 V, −2.0 +1.5 % OUT IN OUT T = −40°C to +125°C J REGULATION Line Regulation ∆V /∆V V = (V + 0.4 V) to 5.5 V, T = −40°C to +125°C −0.05 +0.05 %/V OUT IN IN OUT J Load Regulation1 5-Lead TSOT ∆V /∆I I = 100 µA to 150 mA 0.003 %/mA OUT OUT OUT I = 100 µA to 150 mA, T = −40°C to +125°C 0.0075 %/mA OUT J 4-Ball WLCSP ∆V /∆I I = 100 µA to 150 mA 0.002 %/mA OUT OUT OUT I = 100 µA to 150 mA, T = −40°C to +125°C 0.006 %/mA OUT J DROPOUT VOLTAGE2 V I = 10 mA 10 mV DROPOUT OUT I = 10 mA, T = −40°C to +125°C 35 mV OUT J I = 150 mA 105 mV OUT I = 150 mA, T = −40°C to +125°C 160 mV OUT J START-UP TIME3 T V = 3.3 V 150 µs START-UP OUT CURRENT LIMIT THRESHOLD4 I 190 260 400 mA LIMIT UNDERVOLTAGE LOCKOUT UVLO Input Voltage Rising UVLO T = −40°C to +125°C 1.96 V RISE J Input Voltage Falling UVLO T = −40°C to +125°C 1.28 V FALL J Hysteresis UVLO T = −40°C to +125°C 115 mV HYS J THERMAL SHUTDOWN Thermal Shutdown Threshold TS T rising 150 SD J °C Thermal Shutdown Hysteresis TS 15 SD-HYS °C EN INPUT EN Input Logic High V 2.2 V ≤ V ≤ 5.5 V 1.2 V IH IN EN Input Logic Low V 2.2 V ≤ V ≤ 5.5 V 0.4 V IL IN EN Input Leakage Current V EN = IN or GND 0.001 µA I-LEAKAGE EN = IN or GND, T = −40°C to +125°C 1 µA J OUTPUT NOISE OUT 10 Hz to 100 kHz, V = 5 V, V = 3.3 V 9 µV rms NOISE IN OUT 10 Hz to 100 kHz, V = 5 V, V = 2.5 V 9 µV rms IN OUT 10 Hz to 100 kHz, V = 5 V, V = 1.8 V 9 µV rms IN OUT Rev. C | Page 3 of 20 Document Outline FEATURES APPLICATIONS TYPICAL APPLICATION CIRCUITS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS RECOMMENDED SPECIFICATIONS: INPUT AND OUTPUT CAPACITOR ABSOLUTE MAXIMUM RATINGS THERMAL DATA THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION APPLICATIONS INFORMATION CAPACITOR SELECTION Output Capacitor Input Bypass Capacitor Input and Output Capacitor Properties UNDERVOLTAGE LOCKOUT ENABLE FEATURE CURRENT LIMIT AND THERMAL OVERLOAD PROTECTION THERMAL CONSIDERATIONS PCB LAYOUT CONSIDERATIONS OUTLINE DIMENSIONS ORDERING GUIDE NOTES