Datasheet ADP7105 (Analog Devices) - 5

Data Sheet ADP7105 ABSOLUTE MAXIMUM RATINGS Table 3.
board design is required. The value of θJA may vary, depending
Parameter Rating
on PCB material, layout, and environmental conditions. The specified values of θ VIN to GND −0.3 V to +22 V JA are based on a 4-layer, 4 in. × 3 in. circuit board. See JEDEC JESD51-7 and JESD51-9 for detailed VOUT to GND −0.3 V to +20 V information on the board construction. For additional EN/UVLO to GND −0.3 V to VIN information, see the AN-772 Application Note, A Design and PG to GND −0.3 V to VIN Manufacturing Guide for the Lead Frame Chip Scale Package SENSE/ADJ to GND −0.3 V to VOUT (LFCSP), available at www.analog.com. SS to GND −0.3 V to +3.6 V Storage Temperature Range −65°C to +150°C ΨJB is the junction-to-board thermal characterization parameter Operating Junction Temperature Range −40°C to +125°C with units of °C/W. The package ΨJB is based on modeling and Soldering Conditions JEDEC J-STD-020 calculation using a 4-layer board. JEDEC JESD51-12, Guidelines for Reporting and Using Electronic Package Thermal Information, Stresses at or above those listed under Absolute Maximum states that thermal characterization parameters are not the same Ratings may cause permanent damage to the product. This is a as thermal resistances. ΨJB measures the component power stress rating only; functional operation of the product at these flowing through multiple thermal paths rather than through a or any other conditions above those indicated in the operational single path as in thermal resistance, θJB. Therefore, ΨJB thermal section of this specification is not implied. Operation beyond paths include convection from the top of the package as wel as the maximum operating conditions for extended periods may radiation from the package, factors that make ΨJB more useful affect product reliability. in real-world applications. Maximum junction temperature (TJ)
THERMAL DATA
is calculated from the board temperature (TB) and power dissipation (PD) using the formula Absolute maximum ratings apply individual y only, not in T combination. The ADP7105 can be damaged when the junction J = TB + (PD × ΨJB) temperature (T See JESD51-8 and JESD51-12 for more detailed information J) limit is exceeded. Monitoring ambient temperature does not guarantee that T about Ψ J is within the specified JB. temperature limits. In applications with high power dissipation
THERMAL RESISTANCE
and poor printed circuit board (PCB) thermal resistance, the maximum ambient temperature may need to be derated. θJA and ΨJB are specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. In applications with moderate power dissipation and low PCB θJC is a parameter for surface-mount packages with top thermal resistance, the maximum ambient temperature can mounted heat sinks. θJC is presented here for reference only. exceed the maximum limit as long as the junction temperature is within specification limits. The junction temperature (T
Table 4. Thermal Resistance
J) of the device is dependent on the ambient temperature (T
Package Type θ θ Ψ Unit
A), the
JA JC JB
power dissipation of the device (PD), and the junction-to-ambient 8-Lead LFCSP 40.1 27.1 17.2 °C/W thermal resistance of the package (θJA). 8-Lead SOIC 48.5 58.4 31.3 °C/W Maximum junction temperature (TJ) is calculated from the
ESD CAUTION
ambient temperature (TA) and power dissipation (PD) using the formula TJ = TA + (PD × θJA) Junction-to-ambient thermal resistance (θJA) of the package is based on modeling and calculation using a 4-layer board. The junction-to-ambient thermal resistance is highly dependent on the application and board layout. In applications where high maximum power dissipation exists, close attention to thermal Rev. C | Page 5 of 26 Document Outline Features Applications Typical Application Circuits General Description Table of Contents Revision History Specifications Input and Output Capacitor, Recommended Specifications Absolute Maximum Ratings Thermal Data Thermal Resistance ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Theory of Operation Applications Information Capacitor Selection Output Capacitor Input Bypass Capacitor Input and Output Capacitor Properties Programmable Undervoltage Lockout (UVLO) Soft Start Function Power-Good Feature Noise Reduction of the Adjustable ADP7105 Current-Limit and Thermal Overload Protection Thermal Considerations Printed Circuit Board Layout Considerations Outline Dimensions Ordering Guide