Datasheet ADM7151 (Analog Devices) - 6
| Fabricante | Analog Devices |
| Descripción | 800 mA Ultralow Noise, High PSRR, RF Linear Regulator |
| Páginas / Página | 24 / 6 — ADM7151. Data Sheet. PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS. VREG … |
| Revisión | B |
| Formato / tamaño de archivo | PDF / 1.2 Mb |
| Idioma del documento | Inglés |
ADM7151. Data Sheet. PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS. VREG 1. 8 VIN. VOUT 2. 7 EN. TOP VIEW. BYP 3. 6 REF. (Not to Scale). GND
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ADM7151 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS VREG 1 8 VIN VREG 1 8 VIN VOUT 2 7 EN ADM7151 VOUT 2 7 EN ADM7151 TOP VIEW BYP 3 TOP VIEW 6 REF BYP 3 (Not to Scale) 6 REF (Not to Scale) GND 5 REF_SENSE GND 4 5 REF_SENSE 4 NOTES NOTES 1. EXPOSED PAD ON THE BOTTOM OF THE PACKAGE. 1. EXPOSED PAD ON THE BOTTOM OF THE PACKAGE. EXPOSED PAD ENHANCES THERMAL PERFORMANCE AND IS EXPOSED PAD ENHANCES THERMAL PERFORMANCE AND IS
4 03
ELECTRICALLY CONNECTED TO GND INSIDE THE PACKAGE. ELECTRICALLY CONNECTED TO GND INSIDE THE PACKAGE.
0 00 0-
CONNECT THE EXPOSED PAD TO THE GROUND PLANE ON
0-
CONNECT THE EXPOSED PAD TO THE GROUND PLANE ON
48
THE BOARD TO ENSURE PROPER OPERATION. THE BOARD TO ENSURE PROPER OPERATION.
11 1148 Figure 3. 8-Lead LFCSP Pin Configuration Figure 4. 8-Lead SOIC Pin Configuration
Table 5. Pin Function Descriptions Pin No. Mnemonic Description
1 VREG Regulated Input Supply to LDO Amplifier. Bypass VREG to GND with a 10 μF or greater capacitor. Do not connect a load to ground. 2 VOUT Regulated Output Voltage. Bypass VOUT to GND with a 10 μF or greater capacitor. 3 BYP Low Noise Bypass Capacitor. Connect a 1 μF capacitor to GND to reduce noise. Do not connect a load to ground. 4 GND Ground Connection. 5 REF_SENSE External Resistor Divider Used to Set the Output Voltage. VOUT = VREF × (R1 + R2)/R2, where VREF = 1.5 V. 6 REF Low Noise Reference Voltage Output. Bypass REF to GND with a 1 μF capacitor. Short REF_SENSE to REF for fixed output voltages. Do not connect a load to ground. 7 EN Enable. Drive EN high to turn on the regulator and drive EN low to turn off the regulator. For automatic startup, connect EN to VIN. 8 VIN Regulator Input Supply. Bypass VIN to GND with a 10 μF or greater capacitor. EP EP Exposed Pad on the Bottom of the Package. Exposed pad enhances thermal performance and is electrically connected to GND inside the package. Connect the exposed pad to the ground plane on the board to ensure proper operation. Rev. B | Page 6 of 24 Document Outline FEATURES APPLICATIONS TYPICAL APPLICATION CIRCUIT GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL DATA THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION APPLICATIONS INFORMATION MODEL SELECTION CAPACITOR SELECTION Output Capacitor Input and VREG Capacitor REF Capacitor BYP Capacitor Capacitor Properties ENABLE (EN) AND UNDERVOLTAGE LOCKOUT (UVLO) START-UP TIME REF, BYP, AND VREG PINS CURRENT-LIMIT AND THERMAL OVERLOAD PROTECTION THERMAL CONSIDERATIONS Thermal Characterization Parameter (ΨJB) PRINTED CIRCUIT BOARD LAYOUT CONSIDERATIONS OUTLINE DIMENSIONS ORDERING GUIDE
4 03
ELECTRICALLY CONNECTED TO GND INSIDE THE PACKAGE. ELECTRICALLY CONNECTED TO GND INSIDE THE PACKAGE.
0 00 0-
CONNECT THE EXPOSED PAD TO THE GROUND PLANE ON
0-
CONNECT THE EXPOSED PAD TO THE GROUND PLANE ON
48
THE BOARD TO ENSURE PROPER OPERATION. THE BOARD TO ENSURE PROPER OPERATION.
11 1148 Figure 3. 8-Lead LFCSP Pin Configuration Figure 4. 8-Lead SOIC Pin Configuration
Table 5. Pin Function Descriptions Pin No. Mnemonic Description
1 VREG Regulated Input Supply to LDO Amplifier. Bypass VREG to GND with a 10 μF or greater capacitor. Do not connect a load to ground. 2 VOUT Regulated Output Voltage. Bypass VOUT to GND with a 10 μF or greater capacitor. 3 BYP Low Noise Bypass Capacitor. Connect a 1 μF capacitor to GND to reduce noise. Do not connect a load to ground. 4 GND Ground Connection. 5 REF_SENSE External Resistor Divider Used to Set the Output Voltage. VOUT = VREF × (R1 + R2)/R2, where VREF = 1.5 V. 6 REF Low Noise Reference Voltage Output. Bypass REF to GND with a 1 μF capacitor. Short REF_SENSE to REF for fixed output voltages. Do not connect a load to ground. 7 EN Enable. Drive EN high to turn on the regulator and drive EN low to turn off the regulator. For automatic startup, connect EN to VIN. 8 VIN Regulator Input Supply. Bypass VIN to GND with a 10 μF or greater capacitor. EP EP Exposed Pad on the Bottom of the Package. Exposed pad enhances thermal performance and is electrically connected to GND inside the package. Connect the exposed pad to the ground plane on the board to ensure proper operation. Rev. B | Page 6 of 24 Document Outline FEATURES APPLICATIONS TYPICAL APPLICATION CIRCUIT GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL DATA THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION APPLICATIONS INFORMATION MODEL SELECTION CAPACITOR SELECTION Output Capacitor Input and VREG Capacitor REF Capacitor BYP Capacitor Capacitor Properties ENABLE (EN) AND UNDERVOLTAGE LOCKOUT (UVLO) START-UP TIME REF, BYP, AND VREG PINS CURRENT-LIMIT AND THERMAL OVERLOAD PROTECTION THERMAL CONSIDERATIONS Thermal Characterization Parameter (ΨJB) PRINTED CIRCUIT BOARD LAYOUT CONSIDERATIONS OUTLINE DIMENSIONS ORDERING GUIDE