Datasheet ADP7156 (Analog Devices)

1.2 A, Ultralow Noise, High PSRR, RF Linear Regulator Data Sheet ADP7156 FEATURES TYPICAL APPLICATION CIRCUIT Input voltage range: 2.3 V to 5.5 V ADP7156 16 standard voltages between 1.2 V and 3.3 V available VIN = 3.8V VOUT = 3.3V VIN VOUT Maximum load current: 1.2 A CIN COUT Low noise 10µF 10µF VOUT_SENSE 0.9 µV rms total integrated noise from 100 Hz to 100 kHz ON 1.6 µV rms total integrated noise from 10 Hz to 100 kHz EN OFF REF Noise spectral density: 1.7 nV/√Hz from 10 kHz to 1 MHz C BYP REF C 1µF Power supply rejection ratio (PSRR) BYP 1µF REF_SENSE 80 dB from 1 kHz to 100 kHz; 60 dB at 1 MHz, VOUT = 3.3 V, VREG C V REG IN = 4.0 V 1µF GND (EPAD) Dropout voltage: 120 mV typical at IOUT = 1.2 A, VOUT = 3.3 V
001
Initial accuracy: ±0.6% at ILOAD = 10 mA
12937-
Initial accuracy over line, load, and temperature: ±1.5%
Figure 1.
Quiescent current: IGND = 4.0 mA at no load, 7 mA at 1.2 A Table 1. Related Devices Low shutdown current: 0.2 μA Input Output Fixed/ Stable with a 10 µF ceramic output capacitor Model Voltage Current Adj1 Package 10-lead, 3 mm × 3 mm LFCSP and 8-lead SOIC packages
ADP7158, 2.3 V to 5.5 V 2 A Fixed/ 10-lead LFCSP/
Precision enable
ADP7159 Adj 8-lead SOIC
Supported by ADIsimPower t ool
ADP7157 2.3 V to 5.5 V 1.2 A Fixed/ 10-lead LFCSP/ Adj 8-lead SOIC
APPLICATIONS
ADM7150, 4.5 V to 16 V 800 mA Fixed/ 8-lead LFCSP/
Regulation to noise sensitive applications: phase-locked
ADM7151 Adj 8-lead SOIC
loops (PLLs), voltage controlled oscillators (VCOs), and
ADM7154, 2.3 V to 5.5 V 600 mA Fixed/ 8-lead LFCSP/
PLLs with integrated VCOs
ADM7155 Adj 8-lead SOIC ADM7160 2.2 V to 5.5 V 200 mA Fixed 6-lead LFCSP/
Communications and infrastructure
5-lead TSOT
Backhaul and microwave links
1 Adj means adjustable.
GENERAL DESCRIPTION
The ADP7156 is a linear regulator that operates from 2.3 V to 5.5 V
1k
and provides up to 1.2 A of output current. Using an advanced
CBYP = 1µF z) CBYP = 10µF
proprietary architecture, it provides high power supply rejection
√H CBYP = 100µF C
and ultralow noise, achieving excellent line and load transient
V/ 100 BYP = 1000µF (n
response with only a 10 µF ceramic output capacitor.
Y IT NS
There are 16 standard output voltages for the ADP7156. The
DE 10 L
following voltages are available from stock: 1.2 V, 1.8 V, 2.0 V,
A R T
2.5 V, 2.8 V, 3.0 V and 3.3 V. Additional voltages available by special order are 1.3 V, 1.5 V, 1.6 V, 2.2 V, 2.6 V, 2.7 V, 2.9 V,
1
3.1 V, and 3.2 V.
ISE SPEC O N
The ADP7156 regulator typical output noise is 0.9 μV rms 002 from 100 Hz to 100 kHz and 1.7 nV/√Hz for noise spectral
0.1
12937- density from 10 kHz to 1 MHz. The ADP7156 is available in a
10 100 1k 10k 100k 1M 10M FREQUENCY (Hz)
10-lead, 3 mm × 3 mm LFCSP and 8-lead SOIC packages, Figure 2. Noise Spectral Density at Different Values of CBYP, VOUT = 3.3 V making it not only a very compact solution, but also providing excel ent thermal performance for applications requiring up to 1.2 A of output current in a small, low profile footprint.
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Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TYPICAL APPLICATION CIRCUIT REVISION HISTORY SPECIFICATIONS INPUT AND OUTPUT CAPACITORS, RECOMMENDED SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL DATA THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION APPLICATIONS INFORMATION ADIsimPOWER DESIGN TOOL CAPACITOR SELECTION Output Capacitor Input and VREG Capacitor REF Capacitor BYP Capacitor Capacitor Properties UNDERVOLTAGE LOCKOUT (UVLO) PROGRAMMABLE PRECISION ENABLE START-UP TIME REF, BYP, AND VREG PINS CURRENT-LIMIT AND THERMAL SHUTDOWN THERMAL CONSIDERATIONS Thermal Characterization Parameter (ΨJB) PRINTED CIRCUIT BOARD (PCB) LAYOUT CONSIDERATIONS OUTLINE DIMENSIONS ORDERING GUIDE