Datasheet ADP7158 (Analog Devices) - 5

Data Sheet ADP7158 ABSOLUTE MAXIMUM RATINGS Table 4.
Junction to ambient thermal resistance (θJA) of the package is
Parameter Rating
based on modeling and calculation using a 4-layer board. The junction to ambient thermal resistance is highly dependent on VIN to Ground −0.3 V to +7 V the application and board layout. In applications where high VREG to Ground −0.3 V to VIN, or +4 V (whichever is less) maximum power dissipation exists, close attention to thermal VOUT to Ground −0.3 V to V board design is required. The value of θJA may vary, depending REG, or +4 V (whichever is less) on PCB material, layout, and environmental conditions. The VOUT_SENSE to Ground −0.3 V to VREG, or +4 V specified values of θJA are based on a 4-layer, 4 in. × 3 in. circuit (whichever is less) board. See JESD51-7 and JESD51-9 for detailed information on VOUT to VOUT_SENSE ±0.3 V the board construction. BYP to VOUT ±0.3 V ΨJB is the junction to board thermal characterization parameter EN to Ground −0.3 V to +7 V with units of °C/W. ΨJB of the package is based on modeling and BYP to Ground −0.3 V to VREG, or +4 V calculation using a 4-layer board. JESD51-12, Guidelines for (whichever is less) Reporting and Using Electronic Package Thermal Information, REF to Ground −0.3 V to VREG, or +4 V (whichever is less) states that thermal characterization parameters are not the same REF_SENSE to Ground −0.3 V to +4 V as thermal resistances. ΨJB measures the component power Storage Temperature Range −65°C to +150°C flowing through multiple thermal paths rather than a single Operational Junction Temperature −40°C to +125°C path as in thermal resistance, θJB. Therefore, ΨJB thermal paths Range include convection from the top of the package as well as Soldering Conditions JEDEC J-STD-020 radiation from the package, factors that make ΨJB more useful in real-world applications. Maximum junction temperature (T Stresses at or above those listed under Absolute Maximum J) is calculated from the board temperature (T Ratings may cause permanent damage to the product. This is a B) and power dissipation (P stress rating only; functional operation of the product at these D) using the following formula: or any other conditions above those indicated in the operational TJ = TB + (PD × ΨJB) section of this specification is not implied. Operation beyond See JESD51-8 and JESD51-12 for more detailed information the maximum operating conditions for extended periods may about ΨJB. affect product reliability.
THERMAL RESISTANCE THERMAL DATA
θJA, θJC, and ΨJB are specified for the worst case conditions, that Absolute maximum ratings apply individually only, not in is, a device soldered in a circuit board for surface-mount combination. The ADP7158 can be damaged when the junction packages. temperature limits are exceeded. Monitoring ambient tempera- ture does not guarantee that T
Table 5. Thermal Resistance
J is within the specified temperature limits. In applications with high power dissipation and poor
Package Type θJA θJC ΨJB Unit
thermal resistance, the maximum ambient temperature may 10-Lead LFCSP 53.8 15.6 29.1 °C/W need to be derated. 8-Lead SOIC 50.4 42.3 30.1 °C/W In applications with moderate power dissipation and low printed circuit board (PCB) thermal resistance, the maximum
ESD CAUTION
ambient temperature can exceed the maximum limit as long as the junction temperature is within specification limits. The junction temperature (TJ) of the device is dependent on the ambient temperature (TA), the power dissipation of the device (PD), and the junction to ambient thermal resistance of the package (θJA). Calculate the maximum junction temperature (TJ) from the ambient temperature (TA) and power dissipation (PD) using the following formula: TJ = TA + (PD × θJA) Rev. C | Page 5 of 22 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TYPICAL APPLICATION CIRCUIT TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS INPUT AND OUTPUT CAPACITORS, RECOMMENDED SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL DATA THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION APPLICATIONS INFORMATION ADIsimPower DESIGN TOOL CAPACITOR SELECTION Output Capacitor Input and VREG Capacitor REF Capacitor BYP Capacitor Capacitor Properties UVLO PROGRAMMABLE PRECISION ENABLE START-UP TIME REF, BYP, AND VREG PINS CURRENT LIMIT AND THERMAL SHUTDOWN THERMAL CONSIDERATIONS Thermal Characterization Parameter (ΨJB) PCB LAYOUT CONSIDERATIONS OUTLINE DIMENSIONS ORDERING GUIDE