Datasheet AD96685, AD96687 (Analog Devices) - 3

AD96685/AD96687 ABSOLUTE MAXIMUM RATINGS1 EXPLANATION OF TEST LEVELS
Positive Supply Voltage (+VS) . 6.5 V Test Level Negative Supply Voltage (–V I – 100% production tested. S) . –6.5 V Input Voltage Range2 . ± 5 V II – 100% production tested at 25°C, and sample tested at Differential Input Voltage . 5.5 V specified temperatures. Latch Enable Voltage . –VS to 0 V III – Sample tested only. Output Current . 30 mA IV – Parameter is guaranteed by design and characterization Operating Temperature Range3 testing. AD96685BR/AD96687BQ/BR/BP . –25°C to +85°C Storage Temperature Range . –55°C to +150°C V – Parameter is a typical value only. Junction Temperature . 175°C VI – All devices are 100% production tested at 25°C; 100% Lead Soldering Temperature (10 sec) . 300°C production tested at temperature extremes for extended temperature devices; sample tested at temperature ex- NOTES 1Absolute maximum ratings are limiting values, may be applied individually, and tremes for commercial/industrial devices. beyond which serviceability of the circuit may be impaired. Functional operation under any of these conditions is not necessarily implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2Under no circumstances should the input voltages exceed the supply voltages. 3Typical thermal impedances . AD96685 SOIC qJA = 170°C/W; qJC = 60°C/W AD96687 Ceramic qJA = 115°C/W; qJC = 57°C/W AD96687 SOIC qJA = 92°C/W; qJC = 47°C/W AD96687 PLCC qJA = 81°C/W; qJC = 45°C/W
FUNCTIONAL DESCRIPTION Pin Name Description
+VS Positive supply terminal, nominally 5.0 V. NONINVERTING INPUT Noninverting analog input of the differential input stage. The NONINVERTING INPUT must be driven in conjunction with the INVERTING INPUT. INVERTING INPUT Inverting analog input of the differential input stage. The INVERTING INPUT must be driven in conjunction with the NONINVERTING INPUT. LATCH ENABLE In the “compare” mode (logic HIGH), the output will track changes at the input of the compara- tor. In the “latch” mode (logic LOW), the output will reflect the input state just prior to the comparator being placed in the “latch” mode. LATCH ENABLE must be driven in conjunction with LATCH ENABLE for the AD96687. LATCH ENABLE In the “compare” mode (logic LOW), the output will track changes at the input of the comparator. In the “latch” mode (logic HIGH), the output will reflect the input state just prior to the comparator being placed in the “latch” mode. LATCH ENABLE must be driven in conjunction with LATCH ENABLE for the AD96687. –VS Negative supply terminal, nominally –5.2 V. Q One of two complementary outputs. Q will be at logic HIGH if the analog voltage at the NONINVERTING INPUT is greater than the analog voltage at the INVERTING INPUT (pro- vided the comparator is in the “compare” mode). See LATCH ENABLE and LATCH ENABLE (AD96687 only) for additional information. Q One of two complementary outputs. Q will be at logic LOW if the analog voltage at the NONINVERTING INPUT is greater than the analog voltage at the INVERTING INPUT (provided the comparator is in the “compare” mode). See LATCH ENABLE and LATCH ENABLE (AD96687 only) for additional information. GROUND 1 One of two grounds, but primarily associated with the digital ground. Both grounds should be connected together near the comparator. GROUND 2 One of two grounds, but primarily associated with the analog ground. Both grounds should be connected together near the comparator. REV. D –3–