Datasheet AD790 (Analog Devices) - 6

AD790 CIRCUIT DESCRIPTION VOUT
The AD790 possesses the overall characteristics of a standard
V H V H
monolithic comparator: differential inputs, high gain and a logic
VOH
output. However, its function is implemented with an architec- ture which offers several advantages over previous comparator designs. Specifically, the output stage alleviates some of the limi- tations of classic “TTL” comparators and provides a symmetric output. A simplified representation of the AD790 circuitry is
VOL
shown in Figure 5.
+IN 0 VOS VLOGIC V = HYSTERESIS VOLTAGE H + V = INPUT OFFSET VOLTAGE A1 OS Q1 IN + 2 – 7 VOUT 3 GND IN + + OUTPUT Av –IN –
Figure 6. Hysteresis Definitions (N, Q Package Pinout) hysteresis range. This built-in hysteresis allows the AD790 to avoid oscillation when an input signal slowly crosses the ground
–
level.
A2 Q2 + SUPPLY VOLTAGE CONNECTIONS GAIN STAGE OUTPUT STAGE GND
The AD790 may be operated from either single or dual supply voltages. Internally, the VLOGIC circuitry and the analog front- Figure 5. AD790 Block Diagram end of the AD790 are connected to separate supply pins. If dual supplies are used, any combination of voltages in which +V The output stage takes the amplified differential input signal and S ≥ V converts it to a single-ended logic output. The output swing is LOGIC – 0.5 V and –VS ≤ 0 may be chosen. For single supply operation (i.e., +V defined by the pull-up PNP and the pull-down NPN. These pro- S = VLOGIC), the supply voltage can be oper- ated between 4.5 V and 7 V. Figure 7 shows some other examples duce inherent rail-to-rail output levels, compatible with CMOS of typical supply connections possible with the AD790. logic, as well as TTL, without the need for clamping to internal bias levels. Furthermore, the pull-up and pull-down levels are
BYPASSING AND GROUNDING
symmetric about the center of the supply range and are refer- Although the AD790 is designed to be stable and free from enced off the VLOGIC supply and ground. The output stage has oscillations, it is important to properly bypass and ground the nearly symmetric dynamic drive capability, yielding equal rise power supplies. Ceramic 0.1 µF capacitors are recommended and fall times into subsequent logic gates. and should be connected directly at the AD790’s supply pins. Unlike classic TTL or CMOS output stages, the AD790 circuit These capacitors provide transient currents to the device during does not exhibit large current spikes due to unwanted current comparator switching. The AD790 has three supply voltage flow between the output transistors. The AD790 output stage pins, +VS, –VS and VLOGIC. It is important to have a common has a controlled switching scheme in which amplifiers A1 and ground lead on the board for the supply grounds and the GND A2 drive the output transistors in a manner designed to reduce pin of the AD790 to provide the proper return path for the the current flow between Q1 and Q2. This also helps minimize supply current. the disturbances feeding back to the input which can cause troublesome oscillations.
LATCH OPERATION
The output high and low levels are well controlled values defined The AD790 has a latch function for retaining input information by V at the output. The comparator decision is “latched” and the LOGIC (5 V), ground and the transistor equivalent Schottky clamps and are compatible with TTL and CMOS logic require- output state is held when Pin 5 is brought low. As long as Pin 5 ments. The fanout of the output stage is shown in TPC 3 for is kept low, the output remains in the high or low state, and standard LSTTL or HCMOS gates. Output drive behavior vs. does not respond to changing inputs. Proper capture of the capacitive load is shown in TPC 2. input signal requires that the timing relationships shown in Figure 4 are followed. Pin 5 should be driven with CMOS or
HYSTERESIS
TTL logic levels. The AD790 uses internal feedback to develop hysteresis about The output of the AD790 will respond to the input when Pin 5 the input reference voltage. Figure 6 shows how the input offset is at a high logic level. When not in use, Pin 5 should be connected voltage and hysteresis terms are defined. Input offset voltage to the positive logic supply. When using dual supplies, it is rec- (VOS) is the difference between the center of the hysteresis ommended that a 510 Ω resistor be placed in series with Pin 5 range and the ground level. This can be either positive or nega- and the driving logic gate to limit input currents during powerup. tive. The hysteresis voltage (VH) is one-half the width of the –6– REV. E