Datasheet ADCMP567 (Analog Devices) - 9

Data Sheet ADCMP567 APPLICATIONS INFORMATION
The ADCMP567 comparators are very high speed devices.
CLOCK TIMING RECOVERY
Consequently, high speed design techniques must be employed Comparators are often used in digital systems to recover clock to achieve the best performance. The most critical aspect of any timing signals. High speed square waves transmitted over a ADCMP567 design is the use of a low impedance ground plane. distance, even tens of centimeters, can become distorted due to A ground plane, as part of a multilayer board, is recommended stray capacitance and inductance. Poor layout or improper for proper high speed performance. Using a continuous con- termination can also cause reflections on the transmission line, ductive plane over the surface of the circuit board can create further distorting the signal waveform. A high speed comparator this, allowing breaks in the plane only for necessary signal can be used to recover the distorted waveform while maintaining a paths. The ground plane provides a low inductance ground, minimum of delay. eliminating any potential differences at different ground points throughout the circuit board caused by ground bounce. A proper
OPTIMIZING HIGH SPEED PERFORMANCE
ground plane also minimizes the effects of stray capacitance on As with any high speed comparator amplifier, proper design and the circuit board. layout techniques should be used to ensure optimal performance It is also important to provide bypass capacitors for the power from the ADCMP567. The performance limits of high speed supply in a high speed application. A 1 μF electrolytic bypass circuitry can easily be a result of stray capacitance, improper capacitor should be placed within 0.5 inches of each power supply ground impedance, or other layout issues. pin to ground. These capacitors will reduce any potential voltage Minimizing resistance from source to the input is an important ripples from the power supply. In addition, a 10 nF ceramic consideration in maximizing the high speed operation of the capacitor should be placed as close as possible from the power ADCMP567. Source resistance in combination with equivalent supply pins on the ADCMP567 to ground. These capacitors act input capacitance could cause a lagged response at the input, as a charge reservoir for the device during high frequency thus delaying the output. The input capacitance of the ADCMP567 switching. in combination with stray capacitance from an input pin to The LATCH ENABLE input is active low (latched). If the ground could result in several picofarads of equivalent capacitance. latching function is not used, the LATCH ENABLE input A combination of 3 kΩ source resistance and 5 pF of input should be attached to V capacitance yields a time constant of 15 ns, which is significantly DD (VDD is a PECL logic high), and the complementary input, LATCH ENABLE, should be tied to slower than the sub 500 ps capability of the ADCMP567. Source V impedances should be significantly less than 100 Ω for best DD − 2.0 V. This will disable the latching function. performance. Occasionally, one of the two comparator stages within the ADCMP567 will not be used. The inputs of the unused comparator Sockets should be avoided due to stray capacitance and induc- should not be allowed to float. The high internal gain may cause tance. If proper high speed techniques are used, the ADCMP567 the output to oscillate (possibly affecting the comparator that is should be free from oscillation when the comparator input signal being used) unless the output is forced into a fixed state. This is passes through the switching threshold. easily accomplished by ensuring that the two inputs are at least
COMPARATOR PROPAGATION DELAY
one diode drop apart, while also appropriately connecting the
DISPERSION
LATCH ENABLE and LATCH ENABLE inputs as described The ADCMP567 has been specifically designed to reduce above. propagation delay dispersion over an input overdrive range of The best performance is achieved with the use of proper PECL 100 mV to 1 V. Propagation delay overdrive dispersion is the terminations. The open emitter outputs of the ADCMP567 are change in propagation delay that results from a change in the designed to be terminated through 50 Ω resistors to VDD −2.0 V, degree of overdrive (how far the switching point is exceeded by or any other equivalent PECL termination. If high speed PECL the input). The overall result is a higher degree of timing accuracy signals must be routed more than a centimeter, microstrip or since the ADCMP567 is far less sensitive to input variations than stripline techniques may be required to ensure proper transition most comparator designs. times and prevent output ringing. Propagation delay dispersion is a specification that is important in critical timing applications such as ATE, bench instruments, and nuclear instrumentation. Overdrive dispersion is defined Rev. A | Page 9 of 14 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS THERMAL CONSIDERATIONS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TIMING INFORMATION APPLICATIONS INFORMATION CLOCK TIMING RECOVERY OPTIMIZING HIGH SPEED PERFORMANCE COMPARATOR PROPAGATION DELAY DISPERSION COMPARATOR HYSTERESIS MINIMUM INPUT SLEW RATE REQUIREMENT TYPICAL APPLICATION CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS OUTLINE DIMENSIONS ORDERING GUIDE