Datasheet ADCMP604, ADCMP605 (Analog Devices) - 10

ADCMP604/ADCMP605 Data Sheet APPLICATIONS INFORMATION POWER/GROUND LAYOUT AND BYPASSING LVDS-COMPATIBLE OUTPUT STAGE
The ADCMP604/ADCMP605 comparators are very high speed Specified propagation delay dispersion performance is only devices. Despite the low noise output stage, it is essential to use achieved by keeping parasitic capacitive loads at or below the proper high speed design techniques to achieve the specified specified minimums. The outputs of the ADCMP604 and performance. Because comparators are uncompensated amplifiers, ADCMP605 are designed to directly drive any standard feedback in any phase relationship is likely to cause oscil ations LVDS-compatible input. or undesired hysteresis. The use of low impedance supply planes is
USING/DISABLING THE LATCH FEATURE
of critical importance particularly the output supply plane (VCCO) and the ground plane (GND). Individual supply planes are The latch input is designed for maximum versatility. It can safely be recommended as part of a multilayer board. Providing the left floating or it can be driven low by any standard TTL/CMOS lowest inductance return path for switching currents ensures device as a high speed latch. In addition, the pin can be operated as the best possible performance in the target application. a hysteresis control pin with a bias voltage of 1.25 V nominal and an input resistance of approximately 70 kΩ. This allows the It is also important to adequately bypass the input and output comparator hysteresis to be easily controlled by either a resistor or supplies. Multiple high quality 0.01 µF bypass capacitors should an inexpensive CMOS DAC. Driving this pin high or floating the be placed as close as possible to each of the VCCI and VCCO supply pin disables all hysteresis. pins and should be connected to the GND plane with redundant vias. At least one of these should be placed to provide a physical y Hysteresis control and latch mode can be used together if an short return path for output currents flowing back from ground open drain, an open collector, or a three-state driver is connected in to the V parallel to the hysteresis control resistor or current source. CCI pin and the VCCO pin. High frequency bypass capacitors should be carefully selected for minimum inductance and ESR. Due to the programmable hysteresis feature, the logic threshold Parasitic layout inductance should also be strictly controlled to of the latch pin is approximately 1.1 V, regardless of VCCO. maximize the effectiveness of the bypass at high frequencies.
OPTIMIZING PERFORMANCE
If the package allows, and the input and output supplies have As with any high speed comparator, proper design and layout been connected separately (VCCI ≠ VCCO), be sure to bypass each techniques are essential for obtaining the specified performance. of these supplies separately to the GND plane. Do not connect a Stray capacitance, inductance, inductive power and ground bypass capacitor between these supplies. It is recommended that impedances, or other layout issues can severely limit performance the GND plane separate the VCCI and VCCO planes when the and often cause oscillation. Large discontinuities along input circuit board layout is designed to minimize coupling between and output transmission lines can also limit the specified the two supplies to take advantage of the additional bypass pulse-width dispersion performance. The source impedance capacitance from each respective supply to the ground plane. should be minimized as much as is practicable. High source This enhances the performance when split input/output supplies impedance, in combination with the parasitic input capacitance are used. If the input and output supplies are connected together of the comparator, causes an undesirable degradation in bandwidth for single-supply operation (VCCI = VCCO), coupling between the at the input, thus degrading the overall response. Thermal noise two supplies is unavoidable; however, careful board placement from large resistances can easily cause extra jitter with slowly can help keep output return currents away from the inputs. slewing input signals. Higher impedances encourage undesired coupling. Rev. C | Page 10 of 14 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ELECTRICAL CHARACTERISTICS TIMING INFORMATION ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS APPLICATIONS INFORMATION POWER/GROUND LAYOUT AND BYPASSING LVDS-COMPATIBLE OUTPUT STAGE USING/DISABLING THE LATCH FEATURE OPTIMIZING PERFORMANCE COMPARATOR PROPAGATION DELAY DISPERSION COMPARATOR HYSTERESIS CROSSOVER BIAS POINTS MINIMUM INPUT SLEW RATE REQUIREMENT TYPICAL APPLICATION CIRCUITS OUTLINE DIMENSIONS ORDERING GUIDE