Datasheet AD8465 (Analog Devices) - 7
| Fabricante | Analog Devices |
| Descripción | Rail-to-Rail, Very Fast, 2.5 V to 5.5 V, Single-Supply LVDS Comparator |
| Páginas / Página | 14 / 7 — Data Sheet. AD8465. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. 9 V. … |
| Revisión | B |
| Formato / tamaño de archivo | PDF / 259 Kb |
| Idioma del documento | Inglés |
Data Sheet. AD8465. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. 9 V. CCO. 8 LE/HYS. CCI. TOP VIEW. 7 S
Línea de modelo para esta hoja de datos
Versión de texto del documento
Data Sheet AD8465 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS EE Q V Q 1 12 1 10 V 1 9 V CCO EE AD8465 V 2 8 LE/HYS CCI TOP VIEW V 3 7 S EE DN 4 5 6 P N V EE V V NOTES 1. FOR BEST THERMAL PERFORMANCE,
003
EXPOSED PAD MUST BE SOLDERED TO THE PCB.
07958- Figure 3. Pin Configuration
Table 5. Pin Function Descriptions Pin No. Mnemonic Description
1 VCCO Output Section Supply. 2 VCCI Input Section Supply. 3, 5, 9, 11 VEE Negative Supply Voltages. 4 VP Noninverting Analog Input. 6 VN Inverting Analog Input. 7 SDN Shutdown. Drive this pin low to shut down the device. 8 LE/HYS Latch/Hysteresis Control. Bias with resistor or current for hysteresis; drive low to latch. 10 Q Inverting Output. Q is at logic low if the analog voltage at the noninverting input, VP, is greater than the analog voltage at the inverting input, VN, if the comparator is in compare mode. 12 Q Noninverting Output. Q is at logic high if the analog voltage at the noninverting input, VP, is greater than the analog voltage at the inverting input, VN, if the comparator is in compare mode. 0 EPAD Exposed Pad. The metallic back surface of the package is electrically connected to VEE. It can be left floating because Pin 3, Pin 5, Pin 9, and Pin 11 provide adequate electrical connection. It can also be soldered to the application board if improved thermal and/or mechanical stability is desired. Rev. B | Page 7 of 14 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ELECTRICAL CHARACTERISTICS TIMING INFORMATION ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS APPLICATION INFORMATION POWER/GROUND LAYOUT AND BYPASSING LVDS-COMPATIBLE OUTPUT STAGE USING/DISABLING THE LATCH FEATURE OPTIMIZING PERFORMANCE COMPARATOR PROPAGATION DELAY DISPERSION COMPARATOR HYSTERESIS CROSSOVER BIAS POINTS MINIMUM INPUT SLEW RATE REQUIREMENT TYPICAL APPLICATION CIRCUITS OUTLINE DIMENSIONS ORDERING GUIDE AUTOMOTIVE PRODUCTS
003
EXPOSED PAD MUST BE SOLDERED TO THE PCB.
07958- Figure 3. Pin Configuration
Table 5. Pin Function Descriptions Pin No. Mnemonic Description
1 VCCO Output Section Supply. 2 VCCI Input Section Supply. 3, 5, 9, 11 VEE Negative Supply Voltages. 4 VP Noninverting Analog Input. 6 VN Inverting Analog Input. 7 SDN Shutdown. Drive this pin low to shut down the device. 8 LE/HYS Latch/Hysteresis Control. Bias with resistor or current for hysteresis; drive low to latch. 10 Q Inverting Output. Q is at logic low if the analog voltage at the noninverting input, VP, is greater than the analog voltage at the inverting input, VN, if the comparator is in compare mode. 12 Q Noninverting Output. Q is at logic high if the analog voltage at the noninverting input, VP, is greater than the analog voltage at the inverting input, VN, if the comparator is in compare mode. 0 EPAD Exposed Pad. The metallic back surface of the package is electrically connected to VEE. It can be left floating because Pin 3, Pin 5, Pin 9, and Pin 11 provide adequate electrical connection. It can also be soldered to the application board if improved thermal and/or mechanical stability is desired. Rev. B | Page 7 of 14 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ELECTRICAL CHARACTERISTICS TIMING INFORMATION ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS APPLICATION INFORMATION POWER/GROUND LAYOUT AND BYPASSING LVDS-COMPATIBLE OUTPUT STAGE USING/DISABLING THE LATCH FEATURE OPTIMIZING PERFORMANCE COMPARATOR PROPAGATION DELAY DISPERSION COMPARATOR HYSTERESIS CROSSOVER BIAS POINTS MINIMUM INPUT SLEW RATE REQUIREMENT TYPICAL APPLICATION CIRCUITS OUTLINE DIMENSIONS ORDERING GUIDE AUTOMOTIVE PRODUCTS