Datasheet HMC974 (Analog Devices) - 9

link to page 9 link to page 9
Data Sheet HMC974LC3C THEORY OF OPERATION
The HMC974LC3C is a window comparator where the range of
Table 4. Eye Diagram Details
the window is defined with RT as the top of the voltage window
Parameter Value
range and RB as the bottom of the voltage window range. The Bit Rate 5 Gbps comparator has two modes of operation: track mode and latch Pattern Length 215 − 1 mode. While in track mode, the comparator determines three Deterministic Jitter (Peak-to-Peak) 2.15 ps things: Vertical Scale 80 mV/div 1. If the signal is below the window voltage value, RT, and Time Scale 33.3 ps/div above the window voltage value, RB, represented by the WOUTB output.
POWER SEQUENCING
2. If the signal is above the window voltage value RT, which is Use the following supplies sequentially to power up the device: represented by the ORB output. 3. If the signal is below the window voltage value RB, which is 1. VEE represented by the URB output. 2. VCCI and VCCO (if VCCO = VCCI) 3. VCCO (if different than ground) A typical 5 Gbps output eye is shown in Figure 12 with specific details outlined in Table 4. The power-down sequence is the reverse of the previous sequence: 1. VCCO (if different than ground) 2. VCCI and VCCO (if VCCO = VCCI) 3. VEE
IV) D V/
Apply power to the HMC974LC3C before applying the input
0m
signals (WIN and WIT) and remove the input signals (WIN and
E (8 G
WIT) prior to powering it down.
A EDGE SAMPLES T L VO
012
TIME (33.3ps/DIV)
863- 14 Figure 12. Eye Diagram at 5 Gbps Rev. E | Page 9 of 12 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING DIAGRAM ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS INTERFACE SCHEMATICS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION POWER SEQUENCING APPLICATIONS INFORMATION EVALUATION BOARD OUTLINE DIMENSIONS ORDERING GUIDE