Datasheet ADCMP551, ADCMP552, ADCMP553 (Analog Devices) - 6

ADCMP551/ADCMP552/ADCMP553 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS V 1 20 CCO VCCO QA 2 19 QB QA 1 16 QB QA 3 18 QB QA 2 15 QB V 4 ADCMP552 17 CCO VCCO TOP VIEW V 3 14 V CCO CCO LEA 5 16 LEB (Not to Scale) ADCMP551 LEA 4 13 LEB LEA 6 15 LEB TOP VIEW LEA 1 8 AGND LEA 5 (Not to Scale) 12 LEB V 7 14 CCI AGND LEA 2 ADCMP553 7 VCC V 6 11 AGND CCI –INA 8 13 –INB TOP VIEW +INA 3 6 QA –INA 7 10 –INB +INA 9 12 +INB (Not to Scale) –INA 4 5 QA +INA 8 9 +INB HYSA 10 11 HYSB
04722-004 04722-002 04722-003 Figure 2. ADCMP551 16-Lead QSOP Figure 3. ADCMP552 20-Lead QSOP Figure 4. ADCMP553 8-Lead MSOP Pin Configuration Pin Configuration Pin Configuration
Table 3. Pin Function Descriptions Pin No. ADCMP551 ADCMP552 ADCMP553 Mnemonic Description
3, 14 1, 4, 17, 20 VCCO Logic Supply Terminal. 1 2 6 QA One of Two Complementary Outputs for Channel A. QA is logic high if the analog voltage at the noninverting input is greater than the analog voltage at the inverting input (provided the comparator is in the compare mode). See the description of Pin LEA for more information. 2 3 5 QA One of Two Complementary Outputs for Channel A. QA is logic low if the analog voltage at the noninverting input is greater than the analog voltage at the inverting input (provided the comparator is in the compare mode). See the description of Pin LEA for more information. 4 5 2 LEA One of Two Complementary Inputs for Channel A Latch Enable. In compare mode (logic high), the output tracks changes at the input of the comparator. In latch mode (logic low), the output reflects the input state just prior to the comparator being placed into latch mode. LEA must be driven in conjunction with LEA. 5 6 1 LEA One of Two Complementary Inputs for Channel A Latch Enable. In compare mode (logic low), the output tracks changes at the input of the comparator. In latch mode (logic high), the output reflects the input state just prior to the comparator being placed into latch mode. LEA must be driven in conjunction with LEA. 6 7 VCCI Input Supply Terminal. 7 8 4 −INA Inverting Analog Input of the Differential Input Stage for Channel A. The inverting A input must be driven in conjunction with the noninverting A input. 8 9 3 +INA Noninverting Analog Input of the Differential Input Stage for Channel A. The noninverting A input must be driven in conjunction with the inverting A input. 10 HYSA Programmable Hysteresis. 11 HYSB Programmable Hysteresis. 9 12 +INB Noninverting Analog Input of the Differential Input Stage for Channel B. The noninverting B input must be driven in conjunction with the inverting B input. 10 13 −INB Inverting Analog Input of the Differential Input Stage for Channel B. The inverting B input must be driven in conjunction with the noninverting B input. 11 14 8 AGND Analog Ground. 12 15 LEB One of Two Complementary Inputs for Channel B Latch Enable. In compare mode (logic low), the output tracks changes at the input of the comparator. In latch mode (logic high), the output reflects the input state just prior to the comparator being placed into latch mode. LEB must be driven in conjunction with LEB. Rev. B | Page 6 of 15 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL CONSIDERATIONS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TIMING INFORMATION APPLICATIONS INFORMATION CLOCK TIMING RECOVERY OPTIMIZING HIGH SPEED PERFORMANCE COMPARATOR PROPAGATION DELAY DISPERSION COMPARATOR HYSTERESIS MINIMUM INPUT SLEW RATE REQUIREMENT TYPICAL APPLICATION CIRCUITS OUTLINE DIMENSIONS ORDERING GUIDE