Datasheet ADCMP609 (Analog Devices) - 8

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ADCMP609 Data Sheet APPLICATIONS INFORMATION POWER/GROUND LAYOUT AND BYPASSING VLOGIC
The ADCMP609 comparator is a high speed device. Despite the low noise output stage, it is essential to use proper high speed
A1 Q1
design techniques to achieve the specified performance. Because comparators are uncompensated amplifiers, feedback in any phase relationship is likely to cause oscillations or undesired
+IN OUTPUT
hysteresis. Of critical importance is the use of low impedance
AV
supply planes, particularly the output supply plane (V
–IN
CC) and the ground plane. Individual supply planes are recommended as part of a multilayer board. Providing the lowest inductance return path for switching currents ensures the best possible performance
A2 Q2
in the target application. 011
GAIN STAGE OUTPUT STAGE
It is also important to adequately bypass the input and output 06918- supplies. Place a 0.1 µF bypass capacitor as close as possible to Figure 11. Simplified Schematic Diagram of TTL-/CMOS-Compatible Output Stage each VCC supply pin. The capacitor should be connected to the ground plane with redundant vias placed to provide a physical y
OPTIMIZING PERFORMANCE
short return path for output currents flowing back from ground As with any high speed comparator, proper design and layout tech- to the VCC pin. Carefully select high frequency bypass capacitors niques are essential for obtaining the specified performance. Stray for minimum inductance and effective series resistance (ESR). capacitance, inductance, common power and ground impedances, Parasitic layout inductance should also be strictly controlled to or other layout issues can severely limit performance and often maximize the effectiveness of the bypass at high frequencies. cause oscillation. The source impedance should be minimized as
TTL-/CMOS-COMPATIBLE OUTPUT STAGE
much as is practicable. High source impedance, in combination with the parasitic input capacitance of the comparator, causes an To achieve specified propagation delay performance, keep the undesirable degradation in bandwidth at the input, therefore capacitive load at or below the specified minimums. The degrading the overal response. Higher impedances encourage outputs of the ADCMP609 are designed to directly drive one undesired coupling. Schottky TTL or three low power Schottky TTL loads (or an equivalent). For large fan outputs, buses, or transmission lines,
COMPARATOR PROPAGATION DELAY DISPERSION
use an appropriate buffer to maintain the excellent speed and The ADCMP609 comparator is designed to reduce propagation stability of the comparator. delay dispersion over a wide input overdrive range of 10 mV to With the rated 15 pF load capacitance applied, more than half VCC − 1 V. Propagation delay dispersion is the variation in propa- of the total device propagation delay is output stage slew time. gation delay that results from a change in the degree of overdrive Because of this, the total propagation delay decreases as VCC or slew rate, which is how far or how fast the input signal decreases, and instability in the power supply may appear as exceeds the switching threshold. excess delay dispersion. Propagation delay dispersion is a specification that becomes Delay is measured to the 50% point for whatever supply is in important in high speed, time-critical applications, such as data use; therefore, the fastest times are observed with the VCC supply at communication, automatic test and measurement, and instru- 2.5 V, and larger values are observed when driving loads that mentation. It is also important in event-driven applications, such as switch at other levels. pulse spectroscopy, nuclear instrumentation, and medical imaging. Overdrive and input slew rate dispersions are not significantly Dispersion is the variation in propagation delay as the input over- affected by output loading and V drive conditions are changed (see Figure 12 and Figure 13). CC variations. The TTL-/CMOS-compatible output stage is shown in the ADCMP609 dispersion is typically <12 ns as the overdrive varies simplified schematic diagram (Figure 11). Because of its from 10 mV to 125 mV. This specification applies to both positive inherent symmetry and generally good behavior, this output and negative signals because the device has very closely matched stage is readily adaptable for driving various filters and other delays for both positive-going and negative-going inputs, and very unusual loads. low output skews. Note that for repeatable dispersion measure- ments the actual device offset is added to the overdrive. Rev. C | Page 8 of 12 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS APPLICATIONS INFORMATION POWER/GROUND LAYOUT AND BYPASSING TTL-/CMOS-COMPATIBLE OUTPUT STAGE OPTIMIZING PERFORMANCE COMPARATOR PROPAGATION DELAY DISPERSION COMPARATOR HYSTERESIS CROSSOVER BIAS POINT MINIMUM INPUT SLEW RATE REQUIREMENT TYPICAL APPLICATIONS CIRCUITS OUTLINE DIMENSIONS ORDERING GUIDE