Datasheet DS28E18 (Maxim) - 7

link to page 8 DS28E18 1-Wire® to I2C/SPI Bridge with Command Sequencer
Electrical Characteristics (continued)
(Limits are 100% tested at TA = +25°C and TA = +85°C. Limits over the operating temperature range and relevant supply voltage range are guaranteed by design and characterization. Specifications marked GBD are guaranteed by design and not production tested. Specifications to the minimum operating temperature are guaranteed by design and are not production tested. )
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SPI MASTER (Note 25 )
SPD = 0b00 88.9 100 kHz SPI Master Operating SPD = 0b01 333.3 400 f Frequency MCK SPD = 0b10 0.8 1 MHz SPD = 0b11 2.0 2.3 1 SPI Master SCK Period tMCK f μs MCK SCK Output Pulse- t t MCK μs Width High/Low MCH, tMCL 2 MOSI Output Hold Time t 3 × t After SCK Sample Edge MOH 4 MCK μs MOSI Output Valid to t tMCK μs Sample Edge MOV 4 MISO Input Valid to SCK Sample Edge tMIS 50 ns Setup MISO Input to SCK t Sample Edge Hold MIH 50 ns MOSI Transition to SS t Transition SS:SU tMCK μs SS Active to First SCK t × t Edge SS:CLK SPI mode 3 3 4 MCK μs
Note 1:
System requirement.
Note 2:
System requirement. Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery times. The specified value here applies to systems with only one device and with the minimum 1-Wire recovery times.
Note 3:
Guaranteed by design and/or characterization only. Not production tested.
Note 4:
Value represents the internal parasite capacitance when VPUP is first applied. Once the parasite capacitance is charged, it does not affect normal communication. Typically, during normal communication, the internal parasite capacitance is effectively ~100pF.
Note 5:
VTL, VTH, and VHY are a function of the internal supply voltage, which is a function of VPUP, RPUP, 1-Wire timing, and capacitive loading on IO. Lower VPUP, higher RPUP, shorter tREC, and heavier capacitive loading all lead to lower values of VTL, VTH, and VHY.
Note 6:
Voltage below which, during a falling edge on IO, a logic-zero is detected.
Note 7:
The voltage on IO must be less than or equal to VILMAX at all times the master is driving IO to a logic-zero level.
Note 8:
Voltage above which, during a rising edge on IO, a logic-one is detected.
Note 9:
After VTH is crossed during a rising edge on IO, the voltage on IO must drop by at least VHY to be detected as logic-zero.
Note 10:
The current-voltage (I-V) characteristic is linear for voltages less than 1V.
Note 11:
Applies to a single device attached to a 1-Wire line.
Note 12:
tREC (min) covers operation at worst-case temperature. VPUP, RPUP, CIO, tRSTL, tWOL, tRL, and tRECMIN can be significantly reduced under less extreme conditions. Contact the factory for more information.
Note 13:
The earliest recognition of a negative edge is possible at tREH after VTH has been previously reached.
Note 14:
Defines the maximum possible bit rate. Equal to 1/(tW0LMIN + tRECMIN).
Note 15:
An additional reset or communication sequence cannot begin until the reset high time has expired. 19-100832 www.maximintegrated.com Maxim Integrated | 7 Document Outline General Description Applications Benefits and Features Simplified Application Block Diagram Absolute Maximum Ratings Package Information 8 TDFN-EP Electrical Characteristics Electrical Characteristics (continued) Typical Operating Characteristics Pin Configuration DS28E18 Pin Description Functional Diagram Block Diagram Detailed Description 64-Bit ROM ID Power-Up ROM ID Serialization 1-Wire Bus System Hardware Configuration Transaction Sequence Initialization 1-Wire ROM Function Commands Search ROM [F0h] Read ROM [33h] Match ROM [55h] Skip ROM [CCh] Resume [A5h] Overdrive-Skip ROM [3Ch] Overdrive-Match ROM [69h] 1-Wire Signaling and Timing Read/Write Time Slots Master-to-Slave Slave-to-Master Improved Network Behavior Device Function Commands Command Start (66h) Write Sequencer Command (11h) Read Sequencer Command (22h) Run Sequencer Command (33h) Device Configuration and Status Commands Write Configuration Command (55h) Read Configuration Command (6Ah) Write GPIO Configuration (83h) Read GPIO Configuration (7Ch) Device Status Command (7Ah) Sequencer Commands I2C Sequencer Interface Commands I2C Start Command I2C Stop Command I2C Write Data Command I2C Read Data Command I2C Read Data with NACK End Command SPI Sequencer Commands SPI Write/Read Byte(s) Command SPI Write/Read Bit(s) Command SS_HIGH Command SS_LOW Command Sequencer Utility Commands GPIO_CTRL Write Command GPIO_CTRL Read Command GPIO_BUF Write Command GPIO_BUF Read Command Delay Command SENS_VDD On Command SENS_VDD Off Command I2C Overview I2C Definitions Bus Idle or Not Busy START Condition STOP Condition Repeated START Condition Data Valid SPI Overview SPI Timing SPI Timing Diagram Power-Up of GPIO/I2C Pins Timeout Typical Application Circuits DS28E18 Configured as an I2C Master Typical Application Circuits (continued) DS28E18 Configured as an SPI Master Ordering Information Revision History