Datasheet ADN8831 (Analog Devices) - 7

Data Sheet ADN8831 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS E E T T H C A A M M C I I E E B G G L L T S F N P I V V TI C L L L 32 31 30 29 28 27 26 25 ILIMC 1 24 COMPSW IN1P 2 23 SFB IN1N 3 22 PGND OUT1 4 ADN8831 21 SNGATE IN2P 5 TOP VIEW 20 SW IN2N 6 (Not to Scale) 19 SPGATE OUT2 7 18 PVDD VREF 8 17 COMPOSC 9 10 11 12 13 14 15 16 D E D D Q B O D D S G N E S C S V A P / G R N /I A H F S C P M A S Y T S N Y S NOTES 1. EXPOSED PAD. THE LFCSP HAS AN EXPOSED PAD THAT MUST BE CONNECTED TO AGND (PIN 12) AND
02
THE ASSOCIATED PRINTED CIRCUIT BOARD
-0
(PCB) GROUND PLANE.
04663 Figure 3. Pin Configuration
Table 4. Pin Function Descriptions Pin No. Mnemonic Type Description
1 ILIMC Analog Input Sets TEC Cooling Current Limit. 2 IN1P Analog Input Noninverting Input to Error Amplifier. 3 IN1N Analog Input Inverting Input to Error Amplifier. 4 OUT1 Analog Output Output of Error Amplifier. 5 IN2P Analog Input Noninverting Input to Compensation Amplifier. 6 IN2N Analog Input Inverting Input to Compensation Amplifier. 7 OUT2 Analog Output Output of Compensation Amplifier. 8 VREF Analog Output 2.5 V Voltage Reference Output. 9 AVDD Power Power for Nondriver Sections. 3.0 V minimum; 5.5 V maximum. 10 PHASE Analog Input Sets SYNCO Clock Phase Relative to SYNCI/SD Clock. 11 TMPGD Digital Output Logic Output. Active high. Indicates when the OUT1 voltage is within ±100 mV of IN2P voltage. 12 AGND Ground Analog Ground. Connect to low noise ground. 13 FREQ Analog Input Sets Switching Frequency with an External Resistor. 14 SS/SB Analog Input Sets Soft Start Time for Output Voltage. Pull low (VTEC = 0 V) to put the ADN8831 into standby mode. 15 SYNCO Digital Output Phase Adjustment Clock Output. Phase set from PHASE pin. Used to drive SYNCI/SD of other ADN8831 devices. 16 SYNCI/SD Digital Input Optional Clock Input. If not connected, clock frequency is set by FREQ pin. Pull low to put the ADN8831 into shutdown mode. Pull high to negate shutdown mode. 17 COMPOSC Analog Output Compensation for Oscillator. Connect to PVDD when in free-run mode, connect to R-C network when in external clock mode. 18 PVDD Power Power for Output Driver Sections. 3.0 V minimum; 5.5 V maximum. 19 SPGATE Analog Output PWM Output Drives External PMOS Gate. 20 SW Analog Input Connects to PWM FET Drains. 21 SNGATE Analog Output PWM Output Drives External NMOS Gate. 22 PGND Ground Power Ground. External NMOS devices connect to PGND. Connect to digital ground. 23 SFB Analog Input PWM Feedback. Connect to the TEC module negative (−) terminal. 24 COMPSW Analog Input Compensation Pin for Switching Amplifier. 25 LPGATE Analog Output Linear Output Drives External PMOS Gate. 26 LNGATE Analog Output Linear Output Drives External NMOS Gate. 27 LFB Analog Input Linear Feedback. Connect to H-Bridge transistor output and current sense resistor. 28 CS Analog Input Linear Feedback. Connect to the TEC module positive (+) terminal. 29 ITEC Analog Output Indicates TEC Current. 30 VTEC Analog Output Indicates TEC Voltage. Rev. C | Page 7 of 18 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM REVISION HISTORY DETAILED BLOCK DIAGRAM SPECIFICATIONS ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION OSCILLATOR CLOCK FREQUENCY Free-Run Operation External Clock Operation Connecting Multiple ADN8831 Devices OSCILLATOR CLOCK PHASE TEMPERATURE LOCK INDICATOR SOFT START ON POWER-UP SHUTDOWN MODE STANDBY MODE TEC VOLTAGE/CURRENT MONITOR Voltage Monitor Current Monitor MAXIMUM TEC VOLTAGE LIMIT Using a DAC Using a Resistor Divider MAXIMUM TEC CURRENT LIMIT APPLICATIONS INFORMATION SIGNAL FLOW THERMISTOR SETUP THERMISTOR AMPLIFIER (Chop1) PID COMPENSATION AMPLIFIER (Chop2) MOSFET DRIVER AMPLIFIER OUTLINE DIMENSIONS ORDERING GUIDE