Datasheet ADN8835 (Analog Devices) - 4

link to page 6 link to page 6
ADN8835 Data Sheet SPECIFICATIONS
VIN = 2.7 V to 5.5 V, TJ = −40°C to +125°C for minimum/maximum specifications, and TA = 25°C for typical specifications, unless otherwise noted.
Table 2. Parameter Symbol Test Conditions/Comments Min Typ Max Unit
POWER SUPPLY Driver Supply Voltage VPVIN 2.7 5.5 V Controller Supply Voltage VVDD 2.7 5.5 V Supply Current IVDD PWM not switching 3.3 5 mA Shutdown Current ISD EN/SY = AGND or VLIM/SD = AGND 350 700 µA Undervoltage Lockout (UVLO) VUVLO VVDD rising 2.45 2.55 2.65 V UVLO Hysteresis UVLOHYST 80 90 100 mV REFERENCE VOLTAGE VVREF IVREF = 0 mA to 10 mA 2.475 2.50 2.525 V LINEAR OUTPUT Output Voltage VLDR ILDR = 0 A Low 0 V High VPVIN V Maximum Source Current ILDR_SOURCE 3.5 A Maximum Sink Current ILDR_SINK 3.5 A On Resistance ILDR = 1.5 A P-MOSFET RDS_PL(ON) VPVIN = 5.0 V 50 70 mΩ VPVIN = 3.3 V 55 85 mΩ N-MOSFET RDS_NL(ON) VPVIN = 5.0 V 45 80 mΩ VPVIN = 3.3 V 50 90 mΩ Leakage Current P-MOSFET ILDR_P_LKG 0.1 10 µA N-MOSFET ILDR_N_LKG 0.1 10 µA Linear Amplifier Gain ALDR 40 V/V LDR Short-Circuit Threshold ILDR_SH_GNDL LDR short to PGNDL, enter hiccup 4 A ILDR_SH_PVIN(L) LDR short to PVIN, enter hiccup −4 A Hiccup Cycle tHICCUP 15 ms PWM OUTPUT Output Voltage VSFB ISFB = 0 A V Low 0.06 × VPVIN V High 0.93 × VPVIN V Maximum Source Current ISW_SOURCE 3.5 A Maximum Sink Current ISW_SINK 3.5 A On Resistance ISW = 1.5 A P-MOSFET RDS_PS(ON) VPVIN = 5.0 V 60 85 mΩ VPVIN = 3.3 V 70 100 mΩ N-MOSFET RDS_NS(ON) VPVIN = 5.0 V 45 85 mΩ VPVIN = 3.3 V 55 95 mΩ Leakage Current P-MOSFET ISW_P_LKG 0.1 10 µA N-MOSFET ISW_N_LKG 0.1 10 µA SW Node Rise Time1 tSW_R CSW = 1 nF 1 ns PWM Duty Cycle2 DSW 6 93 % SFB Input Bias Current ISFB 1 2 µA PWM OSCILLATOR Internal Oscil ator Frequency fOSC EN/SY high 1.85 2.0 2.15 MHz Rev. B | Page 4 of 27 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY DETAILED FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE MAXIMUM POWER DISSIPATION ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION ANALOG PID CONTROL DIGITAL PID CONTROL POWERING THE CONTROLLER ENABLE AND SHUTDOWN OSCILLATOR CLOCK FREQUENCY External Clock Operation Connecting Multiple ADN8835 Devices TEMPERATURE LOCK INDICATOR SOFT START ON POWER-UP TEC VOLTAGE/CURRENT MONITOR Voltage Monitor Current Monitor MAXIMUM TEC VOLTAGE LIMIT Using a Resistor Divider to Set the TEC Voltage Limit MAXIMUM TEC CURRENT LIMIT Using a Resistor Divider to Set the TEC Current Limit APPLICATIONS INFORMATION SIGNAL FLOW THERMISTOR SETUP THERMISTOR AMPLIFIER (CHOPPER 1) PID COMPENSATION AMPLIFIER (CHOPPER 2) MOSFET DRIVER AMPLIFIERS PWM OUTPUT FILTER REQUIREMENTS Inductor Selection Capacitor Selection INPUT CAPACITOR SELECTION POWER DISSIPATION PWM Regulator Power Dissipation Conduction Loss (PCOND) Switching Losses (PSW) Transition Losses (PTRAN) Linear Regulator Power Dissipation THERMAL CONSIDERATION PCB LAYOUT GUIDELINES BLOCK DIAGRAMS AND SIGNAL FLOW GUIDELINES FOR REDUCING NOISE AND MINIMIZING POWER LOSS General PCB Layout Guidelines PWM Power Stage Layout Guidelines Linear Power Stage Layout Guidelines Placing the Thermistor Amplifier and PID Components EXAMPLE PCB LAYOUT USING TWO LAYERS OUTLINE DIMENSIONS ORDERING GUIDE