Datasheet ADRV9009 (Analog Devices) - 4

ADRV9009 Data Sheet FUNCTIONAL BLOCK DIAGRAM Rx1 ADRV9009 RX1_IN + Rx2 RX1_IN – RX2_IN + RX2_IN – ADC LPF ORx1 SYNCINx± ORX1_IN + ORx2 ORX1_IN – SERDOUTx± ADC ORX2_IN + SERDINx± ORX2_IN – LPF SYNCOUTx± DIGITAL PROCESSING SYSREF_IN± RF_EXT_LO_I/O+ LO DECIMATION GP_INTERRUPT RF_EXT_LO_I/O– SYNTH ARM pFIR M3 AGC RXx_ENABLE DC-OFFSET QEC TXx_ENABLE LOL JESD204B RESET Tx1 CIF/RIF TX1_OUT + TEST Tx2 TX1_OUT – DAC SCLK TX2_OUT + CS LPF TX2_OUT – SDO SDIO DAC LPF GPIOS, AUXADCs, AND AUXDACs CLOCK REF_CLK_IN + GENERATION REF_CLK_IN –
001
GPIO_3P3_x GPIO_x AUXADC_0 THROUGH AUXADC_3
16499- Figure 1. Rev. B | Page 4 of 127 Document Outline Features Applications General Description Revision History Functional Block Diagram Specifications Current and Power Consumption Specifications Timing Diagrams Absolute Maximum Ratings Reflow Profile Thermal Management Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics 75 MHz to 525 MHz Band 650 MHz to 3000 MHz Band 3400 MHz to 4800 MHz Band 5100 MHz to 5900 MHz Band Transmitter Output Impedance Observation Receiver Input Impedance Receiver Input Impedance Terminology Theory of Operation Transmitter Receiver Observation Receiver Clock Input Synthesizers RF PLL Clock PLL SPI JTAG Boundary Scan Power Supply Sequence GPIO_x Pins Auxiliary Converters AUXADC_x Auxiliary DAC x JESD204B Data Interface Applications Information PCB Layout and Power Supply Recommendations Overview PCB Material and Stackup Selection Fanout and Trace Space Guidelines Component Placement and Routing Guidelines Signals with Highest Routing Priority Signals with Second Routing Priority Signals with Lowest Routing Priority RF and JESD204B Transmission Line Layout RF Routing Guidelines Transmitter Balun DC Feed Supplies JESD204B Trace Routing Recommendations Routing Recommendations Stripline Transmission Lines vs. Microstrip Transmission Lines Isolation Techniques Used on the ADRV9009-W/PCBZ Isolation Goals Isolation Between JESD204B Lines RF Port Interface Information RF Port Impedance Data Advanced Design System (ADS) Setup Using the DataAccessComponent and SEDZ File Transmitter Bias and Port Interface General Receiver Path Interface Impedance Matching Network Examples Outline Dimensions Ordering Guide