Datasheet ADRV9008-2 (Analog Devices) - 3

Data Sheet ADRV9008-2 FUNCTIONAL BLOCK DIAGRAM ORX1 ADRV9008-2 ORX1_IN+ ORX2 SYNCIN0± ORX1_IN– ADC SYNCIN1± ORX2_IN+ SERDOUT0± LPF ORX2_IN– SERDOUT1± SERDOUT2± SERDOUT3± ADC SERDIN0± LPF DIGITAL SERDIN1± PROCESSING SERDIN2± DECIMATION SERDIN3± RF_EXT_LO_I/O+ ARM RF LO pFIR SYNCOUT0± RF_EXT_LO_I/O– Cortex-M3 SYNTHESIZER AGC SYNCOUT1± SYSREFIN± DC OFFSET TX1 GP_INTERRUPT TX1_OUT+ QEC TX2 ORXx_ENABLE LOCAL TX1_OUT– TXx_ENABLE OSCILLATOR DAC LEAKAGE TX2_OUT+ RESET JESD204B SCLK LPF TX2_OUT– CS SDO SDIO DAC LPF GPIOs, AUXILIARY ADCs, REF_CLK_IN+ CLOCK AND AUXILIARY DACs GENERATION REF_CLK_IN–
001
GPIO_3p3_x GPIO_x AUXADC_x
16833- Figure 1. Rev. 0 | Page 3 of 95 Document Outline Features Applications General Description Revision History Functional Block Diagram Specifications Current and Power Consumption Specifications Timing Diagrams Absolute Maximum Ratings Reflow Profile Thermal Management Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics 75 MHz to 525 MHz Band 650 MHz to 3000 MHz Band 3400 MHz to 4800 MHz Band 5100 MHz to 5900 MHz Band Transmitter Output Impedance Observation Receiver Input Impedance Terminology Theory of Operation Transmitter Observation Receiver Clock Input Synthesizers RF PLL Clock PLL Serial Peripheral Interface (SPI) JTAG Boundary Scan Power Supply Sequence GPIO_x Pins Auxiliary Converters AUXADC_x Auxiliary DAC x JESD204B Data Interface Applications Information PCB Layout and Power Supply Recommendations Overview PCB Material and Stackup Selection Fanout and Trace Space Guidelines Component Placement and Routing Guidelines Signals with Highest Routing Priority Signals with Second Routing Priority Signals with Lowest Routing Priority RF and JESD204B Transmission Line Layout RF Routing Guidelines Transmitter Balun DC Feed Supplies JESD204B Trace Routing Recommendations Routing Recommendations Stripline Transmission Lines vs. Microstrip Transmission Lines Isolation Techniques Used on the ADRV9008-2W/PCBZ Isolation Goals Isolation Between JESD204B Lines RF Port Interface Information RF Port Impedance Data Advanced Design System (ADS) Setup Using the DataAccessComponent and SEDZ File Transmitter Bias and Port Interface General Observation Receiver Path Interface Impedance Matching Network Example Outline Dimensions Ordering Guide