Datasheet MAX32670 (Maxim) - 7

MAX32670 High Reliability, Ultra-Low Power Microcontroller Powered by Arm Cortex M4 Processor with FPU for Industrial and IoT
Absolute Maximum Ratings
(All voltages with respect to VSS, unless otherwise noted.) ... Output Current (source) by Any GPIO Pin ... -25mA VCORE ... -0.3V to +1.21V Continuous Package Power Dissipation 40 TQFN-EP (multilayer VDD .. -0.3V to +3.63V board) TA = +70°C (derate 35.7mW/°C above 32KIN, 32KOUT, HFXIN, HFXOUT .. -0.3V to VDD + 0.3V +70°C) ..2857.10mW RSTN, GPIO ... -0.3V to VDD + 0.3V Operating Temperature Range ...-40°C to +105°C Total Current into All GPIO Combined (sink) .. 100mA Storage Temperature Range ..-65°C to +150°C VSS .. 100mA Soldering Temperature (reflow) ..+260°C Output Current (sink) by Any GPIO Pin ... 25mA
All voltages with respect to VSS:
(All voltages with respect to VSS, unless otherwise noted.) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Package Information 40 TQFN-EP
Package Code T4055+1 Outline Number 21-0140 Land Pattern Number 90-0016
Thermal Resistance, Single-Layer Board:
Junction to Ambient (θJA) 45°C/W Junction to Case (θJC) 2 °C/W
Thermal Resistance, Four-Layer Board:
Junction to Ambient (θJA) 28°C/W Junction to Case (θJC) 2°C/W For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Electrical Characteristics
(Limits are 100% tested at TA = +25ºC and TA = +105ºC. Limits over the operating temperature range and relevant supply voltage range are guaranteed by design and characterization. Specifications marked GBD are guaranteed by design and not production tested. Specifications to the minimum operating temperature are guaranteed by design and are not production tested.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS POWER / BOTH SINGLE-SUPPLY OPERATION AND DUAL-SUPPLY OPERATION
Supply Voltage VDD 1.71 1.8 3.63 V OVR = [00] 0.855 0.9 0.945 Dual-supply OVR = [01] 0.95 1.0 1.05 V operation Supply Voltage, Core VCORE Default OVR = [10] 1.045 1.1 1.155 No power supply connection for single — supply operation Monitors VDD 1.58 1.71 Power-Fail Reset V V Voltage RST Monitors VCORE during dual-supply 0.77 0.845 operation 19-100782 www.maximintegrated.com Maxim Integrated | 7 Document Outline General Description Applications Benefits and Features Simplified Block Diagram Absolute Maximum Ratings Package Information 40 TQFN-EP Electrical Characteristics Electrical Characteristics (continued) Electrical Characteristics—SPI Electrical Characteristics—SPI (continued) Electrical Characteristics—I2C Electrical Characteristics—I2C (continued) Electrical Characteristics—I2S Slave Pin Configuration 40 TQFN Pin Description 40 TQFN Detailed Description MAX32670 Arm Cortex-M4 Processor with FPU Engine Memory Internal Flash Memory Internal SRAM Clocking Scheme General-Purpose I/O and Special Function Pins Standard DMA Controller Power Management Power Management Unit Active Mode Sleep Mode DeepSleep Mode Backup Mode Storage Mode Real-Time Clock Windowed Watchdog Timer (WWDT) 32-Bit Timer/Counter/PWM (TMR, LPTMR) Serial Peripherals I2C Interface (I2C) Serial Peripheral Interface (SPI) I2S Interface (I2S) UART (UART, LPUART) Security AES True Random Number Generator (TRNG) CRC Module Secure Boot Debug and Development Interface (SWD) Applications Information Bypass Capacitors Ordering Information Revision History