Datasheet LTM4653 (Analog Devices) - 8

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PIN FUNCTIONS PACKAGE ROW AND COLUMN LABELING MAY VARY RUN (F4):
Run Control Pin. A voltage above 1.2V
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
commands the Module to regulate its output voltage.
LAYOUT CAREFULLY.
Undervoltage lockout (UVLO) can be implemented by
VIN (A1-A3, B3):
Power Input Pins. Apply input voltage connecting RUN to the midpoint node formed by a resis- and input decoupling capacitance directly between VIN tor-divider between VIN and GND. RUN features 130mV and a ground (PGND) plane. of hysteresis. See the Applications Information section.
VD (A4, B4, C4):
Drain of the Converter’s Primary Switching
INTVCC (G3):
Internal Regulator, 3.3V Nominal Output. MOSFET. Apply at minimum one 4.7µF high frequency Internal control circuits and MOSFET-drivers derive power ceramic decoupling capacitor directly from VD to PGND. from INTVCC bias. When operating 3.1V < SVIN ≤ 58V, an Give this capacitor higher layout priority (closer proximity LDO generates INTVCC from SVIN when RUN is logic high to the module) than any VIN decoupling capacitors. (RUN > 1.2V). No external decoupling is required. When
SV
RUN is logic low (RUN - GND < 1.2V), the INTV
IN (C3):
Input Voltage Supply for Small-Signal Circuits. CC LDO is SV off, i.e., INTV IN is the input to the INTVCC LDO. Connect SVIN directly CC is unregulated. (Also see EXTVCC.) to VIN. No decoupling capacitor is needed on this pin.
EXTVCC (F3):
External Bias, Auxiliary Input to the INTVCC
PGND (A5, B5, C5, D5, E5, F5, G4-5, H3, H5, J3-5, K4-5,
Regulator. When EXTVCC exceeds 3.2V and SVIN exceeds
L4-5):
Power Ground Pins of the LTM4653. Connect all 5V, the INTVCC LDO derives power from EXTVCC bias pins to the application’s PGND plane. instead of the SVIN path. This technique can reduce LDO losses considerably, resulting in a corresponding reduc-
VOUT (K1-3, L1-3):
Power Output Pins of the LTM4653. tion in module junction temperature. For applications Connect all pins to the application’s power VOUT plane. in which 4V ≤ V Apply the output filter capacitors and the output load OUT ≤ 26.5V, connect EXTVCC to VOUT through a resistor. (See the Applications Information sec- between a power VOUT plane and the application’s tion for resistor value.) When taking advantage of this PGND plane. EXTVCC feature, locally decouple EXTVCC to PGND with
GND (D4):
Ground Pin of the LTM4653. Electrically con- a 1µF ceramic—otherwise, leave EXTVCC open circuit. nect to the application’s PGND plane.
ISETb (F1):
1.5nF Soft-Start Capacitor. Connect ISETb
VOSNS (G1, H1):
Output Voltage Sense and Feedback to ISETa to achieve default soft-start characteristics, if Signal. Connect VOSNS to VOUT at the point of load (POL). desired. See ISETa. Pins G1 and H1 are electrically connected to each other
ISETa (F2):
Accurate 50μA Current Source. Positive input internal to the module, and thus it is only necessary to to the error amplifier. Connect a resistor (R connect one V ISET) from this OSNS pin to VOUT at the POL. The remain- pin to SGND to program the desired LTM4653 output volt- ing VOSNS pin can be used for redundant connectivity or age, V routed to an ICT test point for design-for-test consider- OUT = RISET • 50μA. A capacitor can be connected from ISETa to SGND to soft-start the output voltage and ations, as desired. reduce start-up inrush current. Connect ISETa to ISETb in
SGND (E4, G2, H2):
Signal Ground Pins of the LTM4653. order to achieve default soft-start, if desired. (See ISETb.) Connect Pin H2 to PGND directly under the LTM4653. The In addition, the output of the LTM4653 can track a voltage SGND pins at locations E4 and G2 are electrically con- applied between the ISETa pin and the SGND pins. (See nected to each other internal to the module, and thus it is the Applications Information section.) only necessary to connect one SGND pin to PGND under the module. The remaining SGND pins can be used for redundant connectivity or routed to an ICT test point for design-for-test considerations, as desired. Rev. A 8 For more information www.analog.com Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Test Circuit Decoupling Requirements Operation Operation Operation Applications Information Typical Applications Package Photograph Package Description Typical Application Related Parts