Datasheet LTM4680 (Analog Devices) - 9

LTM4680
ELECTRICAL CHARACTERISTICS The
l
denotes the specifications which apply over the specified internal operating temperature range (Note 2). n is specified as each individual output channel (Note 4). TA = 25°C, VIN = 12V, RUNn = 3.3V, EXTVCC = 0, FREQUENCY_SWITCH = 350kHz and VOUTn commanded to 1.000V unless otherwise noted. Configured with factory-default EEPROM settings and per Test Circuit 1, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VDD33 Regulator
VVDD33 Internal VDD33 Voltage 4.5V < VINTVCC or 4.8V < VEXTVCC 3.2 3.3 3.4 V ILIM VDD33 Current Limit VDD33 = GND, VIN = INTVCC = 4.5V 100 mA VVDD33_OV VDD33 Overvoltage Threshold 3.5 V VVDD33_UV VDD33 Undervoltage Threshold 3.1 V
VDD25 Regulator
VVDD25 Internal VDD25 Voltage 2.5 V ILIM VDD25 Current Limit VDD25 = GND, VIN = INTVCC = 4.5V 80 mA
Oscillator and Phase-Locked Loop (PLL)
fRANGE PLL SYNC Range Synchronized with Falling Edge of SYNC l 300 1000 kHz fOSC Oscillator Frequency Accuracy Frequency Switch = 250.0 to 1000.0 kHz (Note 15) l ±7.5 % VTH(SYNC) SYNC Input Threshold VSYNC Falling 1 V VSYNC Rising 1.5 V VOL(SYNC) SYNC Low Output Voltage ILOAD = 3mA 0.2 0.4 V ILEAK(SYNC) SYNC Leakage Current in Slave Mode 0V ≤ VPIN ≤ 3.6V ±5 µA θSYNC-θ0 SYNC to Ch0 Phase Relationship MFR_PWM_CONFIG[2:0] = 0,2,3 0 Deg Based on the Falling Edge of Sync MFR_PWM_CONFIG[2:0] = 5 60 Deg and Rising Edge of TG0 MFR_PWM_CONFIG[2:0] = 1 90 Deg MFR_PWM_CONFIG[2:0]= 4,6 120 Deg θSYNC-θ1 SYNC to Ch1 Phase Relationship MFR_PWM_CONFIG[2:0] = 3 120 Deg Based on the Falling Edge of Sync MFR_PWM_CONFIG[2:0] = 0 180 Deg and Rising Edge of TG1 MFR_PWM_CONFIG[2:0] = 2,4,5 240 Deg MFR_PWM_CONFIG[2:0] = 1 270 Deg MFR_PWM_CONFIG[2:0] = 6 300 Deg
EEPROM Characteristics
Endurance (Notes 13, 16) 0°C ≤ TJ ≤ 85°C During EEPROM Write Operations l 10,000 Cycles Retention (Notes 13, 16) TJ < 125°C l 10 Years Mass_Write Mass Write Operation Time STORE_USER_ALL, 0°C < TJ < 85°C 440 4100 ms During EEPROM Write Operation
Leakage Current SDA, SCL, ALERT, RUN
IOL Input Leakage Current OV ≤ VPIN ≤ 5.5V l ±5 µA
Leakage Current FAULTn , PGOODn, SHARE_CLK
IGL Input Leakage Current OV ≤ VPIN ≤ 3.6V l ±2 µA
Digital Inputs SCL, SDA, RUNn , FAULT
n VIH Input High Threshold Voltage l 1.35 V VIL Input Low Threshold Voltage l 0.8 V VHYST Input Hysteresis SCL, SDA 0.08 V CPIN Input Capacitance 10 pF
Digital Input WP
IPUWP Input Pull-Up Current WP 10 µA
Open-Drain Outputs SCL, SDA, FAULTn , ALERT, RUNn , SHARE_CLK, PGOODn
VOL Output Low Voltage ISINK = 3mA 0.4 V Rev. B For more information www.analog.com 9 Document Outline Features Applications Typical Application Description Table of Contents Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Simplified Block Diagram Decoupling Requirements Functional Diagram Test Circuits Operation Power Module Introduction Power Module Overview, Major Features EEPROM with ECC Power-Up and Initialization Soft-Start Time-Based Sequencing Voltage-Based Sequencing Shutdown Light-Load Current Operation Switching Frequency and Phase PWM Loop Compensation Output Voltage Sensing INTVCC/EXTVCC Power Output Current Sensing and Sub Milliohm DCR Current Sensing Input Current Sensing PolyPhase Load Sharing External/Internal Temperature Sense RCONFIG (Resistor Configuration) Pins Table 1. VOUTn_CFG Pin Strapping Look-Up Table for the LTM4680’s Output Voltage, Coarse Setting (Not Applicable if MFR_CONFIG_ALL[6] = 1b) Table 2. VTRIMn_CFG Pin Strapping Look-Up Table for the LTM4680’s Output Voltage, Fine Adjustment Setting (Not Applicable if MFR_CONFIG_ALL[6] = 1b) Table 3. FSWPH_CFG Pin Strapping Look-Up Table to Set the LTM4680’s Switching Frequency and Channel Phase-Interleaving Angle (Not Applicable if MFR_CONFIG_ALL[6] = 1b) Table 4. ASEL Pin Strapping Look-Up Table to Set the LTM4680’s Slave Address (Applicable Regardless of MFR_CONFIG_ALL[6] Setting) Table 5. LTM4680 MFR_ADDRESS Command Examples Expressed in 7- and 8-Bit Addressing Fault Detection and Handling Status Registers and ALERT Masking Figure 5. LTM4680 Status Register Summary Mapping Faults to FAULT Pins Power Good Pins CRC Protection Serial Interface Communication Protection Device Addressing Responses to VOUT and IIN/IOUT Faults Output Overvoltage Fault Response Output Undervoltage Response Peak Output Overcurrent Fault Response Responses to Timing Faults Responses to VIN OV Faults Responses to OT/UT Faults Internal Overtemperature Fault Response External Overtemperature and Undertemperature Fault Response Responses to Input Overcurrent and Output Undercurrent Faults Responses to External Faults Fault Logging Bus Timeout Protection Similarity Between PMBus, SMBus and I2C 2-Wire Interface PMBus Serial Digital Interface Table 6. Abbreviations of Supported Data Formats Figure 6. PMBus Timing Diagram Figures 7 to 24 PMBus Protocols PMBus Command Summary PMBus Commands Table 7. PMBus Commands Summary (Note: The Data Format Abbreviations Are Detailed in Table 8) Table 8. Data Format Abbreviations Applications Information VIN to VOUT Step-Down Ratios Input Capacitors Output Capacitors Light Load Current Operation Switching Frequency and Phase Output Current Limit Programming Minimum On-Time Considerations Variable Delay Time, Soft-Start and Output Voltage Ramping Digital Servo Mode Soft Off (Sequenced Off) Undervoltage Lockout Fault Detection and Handling Open-Drain Pins Phase-Locked Loop and Frequency Synchronization Input Current Sense Amplifier Programmable Loop Compensation Checking Transient Response PolyPhase Configuration Connecting The USB to I2C/SMBus/PMBus Controller to the LTM4680 In System LTpowerPlay: An Interactive GUI for Digital Power PMBus Communication and Command Processing Thermal Considerations and Output Current Derating Tables 10 thru 11: Output Current Derating Table 12. Channel Output Voltage vs Capacitor Selection, All Ceramic Configuration, 15A to 30A Load Step with 15A/µs Slew Rate Table 13. Channel Output Voltage vs Capacitor Selection, Bulk and Ceramic Cap Configuration, 15A to 30A Load Step with 15A/µs Slew Rate Table 14. Dual Phase Single Output Voltage vs Capacitor Selection, Bulk and Ceramic Cap Configuration, 30A to 60A Load Step with 30A/µs Slew Rate Derating Curves EMI Performance Safety Considerations Layout Checklist/Example Typical Applications PMBus Command Details Addressing and Write Protect General Configuration Commands On/Off/Margin PWM Configuration Voltage Input Voltage and Limits Output Voltage and Limits Output Current and Limits Input Current and Limits Temperature Power Stage DCR Temperature Calibration Timing Timing—On Sequence/Ramp Timing—Off Sequence/Ramp Precondition for Restart Fault Response Fault Responses All Faults Fault Responses Input Voltage Fault Responses Output Voltage Fault Responses Output Current Fault Responses IC Temperature Fault Responses External Temperature Fault Sharing Fault Sharing Propagation Fault Sharing Response Scratchpad Identification Fault Warning and Status Telemetry NVM Memory Commands Store/Restore Fault Logging Block Memory Write/Read Package Description Table 23. LTM4680 BGA Pinout Revision History Package Photograph Design Resources Related Parts