Datasheet ADuCM3027, ADuCM3029 (Analog Devices) - 9

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Data Sheet ADuCM3027/ ADuCM3029 TIMING SPECIFICATIONS Reset Timing Table 11. Parameter Symbol Min Typ Max Unit
RESET TIMING REQUIREMENTS SYS_HWRST Asserted Pulse Width Low1 tWRST 4 µs 1 Applies after power-up sequence is complete.
tWRST SYS_HWRST
002 14168- Figure 2. Reset Timing
Serial Ports Timing Table 12. Parameter Symbol Min Typ Max Unit Test Conditions/Comments
EXTERNAL CLOCK SERIAL PORTS Timing Requirements Frame Sync Setup Before SPT_CLK1 tSFSE 5 ns Externally generated frame sync in transmit or receive mode Frame Sync Hold After SPT_CLK1 tHFSE 5 ns Externally generated frame sync in transmit or receive mode Receive Data Setup Before Receive SPT_CLK1 tSDRE 5 ns Receive Data Hold After SPT_CLK1 tHDRE 8 ns SPT_CLK Width2 tSCLKW 38.5 ns SPT_CLK Period2 tSPTCLK 77 ns Switching Characteristics3 Frame Sync Delay After SPT_CLK tDFSE 20 ns Internal y generated frame sync in transmit or receive mode Frame Sync Hold After SPT_CLK tHOFSE 2 ns Internal y generated frame sync in transmit or receive mode Transmit Data Delay After Transmit SPT_CLK tDDTE 20 ns Transmit Data Hold After Transmit SPT_CLK tHDTE 1 ns INTERNAL CLOCK SERIAL PORTS Timing Requirements1 Receive Data Setup Before SPT_CLK tSDRI 25 ns Receive Data Hold After SPT_CLK tHDRI 0 ns Switching Characteristics Frame Sync Delay After SPT_CLK 3 tDFSI 20 ns Internal y generated frame sync in transmit or receive mode Frame Sync Hold After SPT_CLK 3 tHOFSI −8 ns Internal y generated frame sync in transmit or receive mode Transmit Data Delay After SPT_CLK3 tDDTI 20 ns Transmit Data Hold After SPT_CLK3 tHDTI −7 ns SPT_CLK Width tSCLKIW tPCLK − 1.5 ns SPT_CLK Period tSPTCLK (2 × tPCLK) − 1 ns Not shown in Figure 3 to Figure 7 ENABLE AND THREE-STATE SERIAL PORTS Switching Characteristics Data Enable from Internal Transmit SPT_CLK3 tDDTIN 5 ns Data Disable from Internal Transmit SPT_CLK3 tDDTTI 160 ns 1 This specification is referenced to the sample edge. 2 This specification indicates the minimum instantaneous width or period that can be tolerated due to duty cycle variation or jitter on the external SPT_CLK. 3 These specifications are referenced to the drive edge. Rev. B | Page 9 of 39 Document Outline Features Applications Functional Block Diagram Revision History General Description Product Highlights Specifications Operating Conditions and Electrical Characteristics Embedded Flash Specifications Power Supply Current Specifications Active Mode Flexi Mode Deep Sleep Modes—VBAT = 3.0 V ADC Specifications System Clocks External Crystal Oscillator Specifications On-Chip RC Oscillator Specifications System Clocks and PLL Specifications Timing Specifications Reset Timing Serial Ports Timing SPI Timing I2C Specifications General-Purpose Port Timing RTC1 (FLEX_RTC) Specifications Timer Pulse-Width Modulation (PWM) Output Cycle Timing Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation ARM Cortex-M3 Processor ARM Cortex-M3 Memory Subsystem Code Region SRAM Region System Region Memory Architecture SRAM Region MMRs (Peripheral Control and Status) Flash Memory Cache Controller System and Integration Features Reset Booting Power Management Power Modes Active Mode Flexi Mode Hibernate Mode Shutdown Mode Security Features Cryptographic Accelerator True Random Number Generator (TRNG) Reliability and Robustness Features ECC Enabled Flash Memory Multiparity Bit Protected SRAM Software Watchdog Cyclic Redundancy Check (CRC) Accelerator Programmable GPIOs Timers General-Purpose Timers Watchdog Timer (WDT) Analog-to-Digital Converter (ADC) Subsystem Clocking Beeper Driver Debug Capability On-Chip Peripheral Features Serial Ports (SPORT) SPI Ports UART Port I2C Development Support Documentation Hardware Software Additional Information Reference Designs MCU Test Conditions Driver Types EEMBC ULPMark™-CP Score GPIO Multiplexing Applications Information About ADuCM3027/ADuCM3029 Silicon Anomalies Functionality Issues Outline Dimensions Ordering Guide