Datasheet ADuCM4050 (Analog Devices) - 5

Data Sheet ADuCM4050 POWER SUPPLY CURRENT SPECIFICATIONS Active Mode Table 3. Parameter Min Typ1 Max2 Unit Test Conditions/Comments
ACTIVE MODE3 Current consumption when VBAT = 3.0 V Buck Enabled 1.27 2.71 mA Code executing from flash, cache enabled, system peripheral clock (PCLK) disabled, advanced high performance clock (HCLK) = 26 MHz4 1.83 3.28 mA Code executing from flash, cache disabled, PCLK disabled, HCLK = 26 MHz4 1.40 2.84 mA Code executing from flash, cache enabled, PCLK = 26 MHz, HCLK = 26 MHz4 1.97 3.41 mA Code executing from flash, cache disabled, PCLK = 26 MHz, HCLK = 26 MHz4 2.33 3.78 mA Code executing from flash, cache enabled, PCLK disabled, HCLK = 52 MHz5 2.94 4.39 mA Code executing from flash, cache disabled, PCLK disabled, HCLK = 52 MHz5 2.59 4.04 mA Code executing from flash, cache enabled, PCLK = 52 MHz, HCLK = 52 MHz5 3.21 4.65 mA Code executing from flash, cache disabled, PCLK = 52 MHz, HCLK = 52 MHz5 1.43 2.87 mA Code executing from SRAM, PCLK disabled, HCLK = 26 MHz4 1.56 3.00 mA Code executing from SRAM, PCLK = 26 MHz, HCLK = 26 MHz4 2.64 4.09 mA Code executing from SRAM, PCLK disabled, HCLK = 52 MHz5 2.90 4.35 mA Code executing from SRAM, PCLK = 52 MHz, HCLK = 52 MHz5 Dynamic Current 41 µA/MHz Code executing from flash, cache enabled Buck Disabled 2.34 4.78 mA Code executing from flash, cache enabled, PCLK disabled, HCLK = 26 MHz4 3.38 5.82 mA Code executing from flash, cache disabled, PCLK disabled, HCLK = 26 MHz4 2.60 5.04 mA Code executing from flash, cache enabled, PCLK = 26 MHz, HCLK = 26 MHz4 3.65 6.09 mA Code executing from flash, cache disabled, PCLK = 26 MHz, HCLK = 26 MHz4 4.46 6.90 mA Code executing from flash, cache enabled, PCLK disabled, HCLK = 52 MHz5 5.61 8.05 mA Code executing from flash, cache disabled, PCLK disabled, HCLK = 52 MHz5 4.98 7.42 mA Code executing from flash, cache enabled, PCLK = 52 MHz, HCLK = 52 MHz5 6.14 8.58 mA Code executing from flash, cache disabled, PCLK = 52 MHz, HCLK = 52 MHz5 2.66 5.10 mA Code executing from SRAM, PCLK disabled, HCLK = 26 MHz4 2.92 5.36 mA Code executing from SRAM, PCLK = 26 MHz, HCLK = 26 MHz4 5.08 7.52 mA Code executing from SRAM, PCLK disabled, HCLK = 52 MHz5 5.60 8.04 mA Code executing from SRAM, PCLK = 52 MHz, HCLK = 52 MHz5 Dynamic Current 82 µA/MHz Code executing from flash, cache enabled 1 TJ = 25°C 2 TJ = 85°C 3 The code being executed is a prime number generation in a continuous loop, with high frequency RC oscillator (HFOSC) as the system clock source. 4 Zero wait states and low buck load. 5 One wait state and high buck load. Rev. A | Page 5 of 46 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM REVISION HISTORY GENERAL DESCRIPTION PRODUCT HIGHLIGHTS SPECIFICATIONS OPERATING CONDITIONS AND ELECTRICAL CHARACTERISTICS EMBEDDED FLASH SPECIFICATIONS POWER SUPPLY CURRENT SPECIFICATIONS Active Mode Flexi Mode Deep Sleep Modes—VBAT = 1.8 V Deep Sleep Modes—VBAT = 3.0 V Deep Sleep Modes—VBAT = 3.6 V ADC SPECIFICATIONS TEMPERATURE SENSOR SPECIFICATIONS SYSTEM CLOCKS External Crystal Oscillator Specifications On-Chip Resistor-Capacitor (RC) Oscillator Specifications System Clocks and Phase-Locked Loop (PLL) Specifications TIMING SPECIFICATIONS Reset Timing Serial Ports Timing SPI Timing I2C Specifications General-Purpose Port Timing RTC1 (FLEX_RTC) Specifications Timer Pulse-Width Modulation (PWM) Output Cycle Timing ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION ARM CORTEX-M4F PROCESSOR ARM Cortex-M4F Subsystem Code Region SRAM Region System Region MEMORY ARCHITECTURE SRAM Region MMRs (Peripheral Control and Status) Flash Memory Cache Controller SYSTEM INTEGRATION FEATURES Reset Booting Power Management and Modes Active Mode Flexi Mode Hibernate Mode Shutdown Mode Shutdown Mode—Fast Wake-Up Power Management and Control Security Features Cryptographic Accelerator True Random Number Generator (TRNG) Reliability and Robustness Features ECC Enabled Flash Memory Multiparity Bit Protected SRAM Software Watchdog CRC Accelerator Programmable GPIOs Timers General-Purpose Timers Watchdog Timer (WDT) RGB Timer ADC Subsystem Clocking Clock Fail Detection Real-Time Clock (RTC) Beeper Driver Debug Capability ON-CHIP PERIPHERAL FEATURES Serial Ports (SPORT) SPI Ports UART Ports I2C DEVELOPMENT SUPPORT Documentation Hardware Software REFERENCE DESIGNS SECURITY FEATURES DISCLAIMER MCU TEST CONDITIONS DRIVER TYPES EEMBC ULPMARK™-CP SCORE GPIO MULTIPLEXING APPLICATIONS INFORMATION SILICON ANOMALY ADuCM4050 FUNCTIONALITY ISSUES FUNCTIONALITY ISSUES SECTION 1. ADuCM4050 FUNCTIONALITY ISSUES OUTLINE DIMENSIONS ORDERING GUIDE