Datasheet AD5590 (Analog Devices) - 10
| Fabricante | Analog Devices |
| Descripción | 16 Input, 16 Output Analog I/O Port with Integrated Amplifiers |
| Páginas / Página | 44 / 10 — AD5590. DAC Timing Characteristics. Table 6. Parameter. Limit at TMIN, … |
| Revisión | A |
| Formato / tamaño de archivo | PDF / 1.0 Mb |
| Idioma del documento | Inglés |
AD5590. DAC Timing Characteristics. Table 6. Parameter. Limit at TMIN, TMAX; DACVDD = 2.7 V to 5.5 V. Unit. Conditions/Comments
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AD5590 DAC Timing Characteristics
All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 4. DACVDD = 4.5 V to 5.5 V. All specifications TMIN to TMAX, unless otherwise noted.
Table 6. Parameter
1
Limit at TMIN, TMAX; DACVDD = 2.7 V to 5.5 V Unit Conditions/Comments
t 2 1 20 ns min DSCLK cycle time t2 8 ns min DSCLK high time t3 8 ns min DSCLK low time t4 13 ns min DSYNC to DSCLK falling edge setup time t5 4 ns min Data setup time t6 4 ns min Data hold time t7 0 ns min DSCLK falling edge to DSYNC rising edge t8 15 ns min Minimum DSYNC high time t9 13 ns min DSYNC rising edge to DSCLK fall ignore t10 0 ns min DSCLK falling edge to DSYNC fall ignore t11 10 ns min LDAC pulse width low t12 15 ns min DSCLK falling edge to LDAC rising edge t13 5 ns min CLR pulse width low t14 0 ns min DSCLK falling edge to LDAC falling edge t15 300 ns typ CLR pulse activation time 1 Sample tested at 25°C to ensure compliance. 2 Maximum DSCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V. Guaranteed by design and characterization; not production tested.
t10 t1 t9 DSCLK t2 t8 t t t7 4 3 DSYNCx t6 t5 DDIN DB31 DB0 t11 t14 LDAC1 t12 LDAC2 CLR t13 t VOUTx 15 1ASYNCHRONOUS LDAC UPDATE MODE.
004
2SYNCHRONOUS LDAC UPDATE MODE.
07691- Figure 4. DAC Timing Characteristics Rev. A | Page 10 of 44 Document Outline Features Applications Functional Block Diagram Revision History General Description Specifications ADC Specifications DAC Specifications DAC AC Characteristics Operational Amplifier Specifications Timing Specifications ADC Timing Characteristics DAC Timing Characteristics Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics DAC ADC Amplifier Terminology Theory of Operation DAC Section Resistor String DAC Internal Reference DAC Output Amplifier ADC Section ADC Converter Operation Analog Input ADC Transfer Function Analog Input Selection Digital Inputs VDRIVE Reference Section Amplifier Section Serial Interface Accessing the DAC Block DAC Input Shift Register Interrupt DAC Internal Reference Register DAC Power-On Reset DAC Power-Down Modes DAC Clear Code Register LDAC Function Accessing the ADC Block ADC Modes of Operation Normal Mode (PM1 = PM0 = 1) Full Shutdown (PM1 = 1, PM0 = 0) AutoShutdown (PM1 = 0, PM0 = 1) Autostandby (PM1 = PM0 = 0) Powering Up the ADC Interfacing to the ADC ADC Control Register ADC Sequencer Operation ADC Shadow Register ADC Power vs. Throughput Rate Outline Dimensions Ordering Guide
AD5590 DAC Timing Characteristics
All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 4. DACVDD = 4.5 V to 5.5 V. All specifications TMIN to TMAX, unless otherwise noted.
Table 6. Parameter
1
Limit at TMIN, TMAX; DACVDD = 2.7 V to 5.5 V Unit Conditions/Comments
t 2 1 20 ns min DSCLK cycle time t2 8 ns min DSCLK high time t3 8 ns min DSCLK low time t4 13 ns min DSYNC to DSCLK falling edge setup time t5 4 ns min Data setup time t6 4 ns min Data hold time t7 0 ns min DSCLK falling edge to DSYNC rising edge t8 15 ns min Minimum DSYNC high time t9 13 ns min DSYNC rising edge to DSCLK fall ignore t10 0 ns min DSCLK falling edge to DSYNC fall ignore t11 10 ns min LDAC pulse width low t12 15 ns min DSCLK falling edge to LDAC rising edge t13 5 ns min CLR pulse width low t14 0 ns min DSCLK falling edge to LDAC falling edge t15 300 ns typ CLR pulse activation time 1 Sample tested at 25°C to ensure compliance. 2 Maximum DSCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V. Guaranteed by design and characterization; not production tested.
t10 t1 t9 DSCLK t2 t8 t t t7 4 3 DSYNCx t6 t5 DDIN DB31 DB0 t11 t14 LDAC1 t12 LDAC2 CLR t13 t VOUTx 15 1ASYNCHRONOUS LDAC UPDATE MODE.
004
2SYNCHRONOUS LDAC UPDATE MODE.
07691- Figure 4. DAC Timing Characteristics Rev. A | Page 10 of 44 Document Outline Features Applications Functional Block Diagram Revision History General Description Specifications ADC Specifications DAC Specifications DAC AC Characteristics Operational Amplifier Specifications Timing Specifications ADC Timing Characteristics DAC Timing Characteristics Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics DAC ADC Amplifier Terminology Theory of Operation DAC Section Resistor String DAC Internal Reference DAC Output Amplifier ADC Section ADC Converter Operation Analog Input ADC Transfer Function Analog Input Selection Digital Inputs VDRIVE Reference Section Amplifier Section Serial Interface Accessing the DAC Block DAC Input Shift Register Interrupt DAC Internal Reference Register DAC Power-On Reset DAC Power-Down Modes DAC Clear Code Register LDAC Function Accessing the ADC Block ADC Modes of Operation Normal Mode (PM1 = PM0 = 1) Full Shutdown (PM1 = 1, PM0 = 0) AutoShutdown (PM1 = 0, PM0 = 1) Autostandby (PM1 = PM0 = 0) Powering Up the ADC Interfacing to the ADC ADC Control Register ADC Sequencer Operation ADC Shadow Register ADC Power vs. Throughput Rate Outline Dimensions Ordering Guide