Datasheet AD7294-2 (Analog Devices) - 10

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AD7294-2 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS C D A INFE /R ) ) 7 6 T U 2 1 (– (+ D D D P O 1 1 N D N A F 0 1 2 3 C P P P P S S C G C V G C E IN IN IN IN N V V R R N A N A A D R V V V V 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 NC 1 48 DGND PIN 1 RS2(–) 2 47 INDICATOR DGND RS2(+) 3 46 ISENSE1 OVERRANGE NC 4 45 ISENSE2 OVERRANGE NC 5 44 RESET AGND1 6 43 DGND AGND2 7 42 V AD7294-2 DRIVE NC 8 41 OPGND TQFP D2(–) 9 TOP VIEW 40 SCL (Not to Scale) D2(+) 10 39 SDA D1(+) 11 38 AS0 D1(–) 12 37 AS1 AGND3 13 36 AS2 FACTORY TEST 14 35 ALERT/BUSY REF 15 34 AGND5 OUT/REFIN DAC NC 16 33 NC 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 C A B B B B 4 C C D D C C D D N A A A N IN T T D T T U U IN IN C C N + N U U IN D + D T O O V T T O N G V N O T E V T V E E V V T E S A G U S S U G S F T F F T F F U O F F O U F O C O O C O A A O O C D D C A A D D
005
NOTES
936-
1. NC = NO INTERNAL CONNECTION.
10 Figure 4. Pin Configuration
Table 7. Pin Function Descriptions Pin No. Mnemonic Description
2, 61 RS2(−), RS1(−) Connection for External Shunt Resistor. 3, 60 RS2(+), RS1(+) Connection for External Shunt Resistor. 1, 4, 5, 8, NC This pin has no internal connection. 16, 17, 25, 32, 33, 57 59, 64 14 FACTORY TEST Factory Test Pin. To maintain pin compatibility with the AD7294, this pin can tolerate being connected to voltages of up to 5.5 V. 56 AVDD Analog Supply Pin. The operating range is 4.5 V to 5.5 V. This pin provides the supply voltage for all the analog circuitry on the AD7294-2. This supply should be decoupled to AGND with one 10 μF tantalum capacitor and a 0.1 μF ceramic capacitor. 6, 7, 13, AGND1 to AGND7 Analog Ground. Ground reference point for all analog circuitry on the AD7294-2. Refer all analog input 24, 34, signals and any external reference signal to this AGND voltage. Connect all seven of these AGND pins to 55, 58 the AGND plane of the system. Note that AGND5 is a DAC ground reference point and should be used as a star ground for circuitry being driven by the DAC outputs. Ideally, the AGND and DGND voltages should be at the same potential and must not be more than 0.3 V apart, even on a transient basis. 9, 12 D2(−), D1(−) Temperature Sensor Analog Inputs. These pins are connected to the external temperature sensing transistor. See Figure 43 and Figure 44. 10, 11 D2(+), D1(+) Temperature Sensor Analog Inputs. These pins are connected to the external temperature sensing transistor. See Figure 43 and Figure 44. 15 REFOUT/REFIN DAC DAC Reference Output/Input Pin. The REFOUT/REFIN DAC pin is common to all four DAC channels. On power-up, the default configuration of this pin is as an external reference (REFIN). Enable the internal reference by writing to the power-down register; see Table 27. Decoupling capacitors (220 nF recommended) are connected to this pin to decouple the reference buffer. If the output is buffered, the on-chip reference can be taken from this pin and applied externally to the rest of a system. A maximum external reference voltage of AVDD − 2 V can be supplied to the REFOUT portion of the REFOUT/REFIN DAC pin. Rev. 0 | Page 10 of 44 Document Outline Features Applications General Description Table of Contents Revision History Functional Block Diagram Specifications DAC Specifications ADC Specifications General Specifications Timing Characteristics I2C Serial Interface Timing and Circuit Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Terminology DAC Terminology ADC Terminology Theory of Operation ADC Overview ADC Transfer Functions Analog Inputs Single-Ended Mode Differential Mode Driving Differential Inputs Using an Op Amp Pair Pseudo Differential Mode Current Sensor Choosing RSENSE Current Sense Filtering Kelvin Sense Resistor Connection Analog Comparator Loop Temperature Sensor Remote Sensing Diode Ideality Factor Base Emitter Voltage hFE Variation Series Resistance Cancellation DAC Operation Resistor String Output Amplifiers ADC and DAC Reference VDRIVE Feature Register Settings Address Pointer Register Command Register ADC Result Register ADC Channel Allocation TSENSE1 and TSENSE2 Result Registers TSENSEINT Result Register Temperature Value Format DACA, DACB, DACC, and DACD Value Registers Alert Status Register A, Alert Status Register B, and Alert Status Register C Channel Sequence Register Configuration Register Sample Delay and Bit Trial Delay Power-Down Register DATALOW and DATAHIGH Registers VIN0 to VIN3 Channels TSENSE1, TSENSE2, and TSENSEINT Channels Hysteresis Registers Remote Channel TSENSE1 and TSENSE2 Offset Registers I2C Interface General I2C Timing Serial Bus Address Byte Interface Protocol Writing a Single Byte of Data to an 8-Bit Register Writing Two Bytes of Data to a 16-Bit Register Writing to Multiple Registers Reading Data from an 8-Bit Register Reading Two Bytes of Data from a 16-Bit Register Modes of Operation Command Mode Autocycle Mode Alerts and Limits Theory ALERT_FLAG Bit Alert Status Registers DATALOW and DATAHIGH Monitoring Features Hysteresis Using the Limit Registers to Store Minimum/Maximum Conversion Results Applications Information Base Station Power Amplifier Monitor and Control Gain Control of Power Amplifier Outline Dimensions Ordering Guide