Datasheet AD74413R (Analog Devices) - 5

Data Sheet AD74413R SPECIFICATIONS VOLTAGE OUTPUT
AVDD = 14 V to 28.8 V, AGND = DGND = 0 V, REFIN = 2.5 V (ideal), DVCC = 2.7 V to 5.5 V, IOVDD = 1.7 V to 5.5 V, and all specifications at TA = −40°C to +105°C, unless otherwise noted. Resistor load (RLOAD) = 100 kΩ and capacitor load (CLOAD) = 10 nF per recommended configuration.
Table 1. Parameter Min Typ Max Unit Test Conditions/Comments
VOLTAGE OUTPUT Resolution 13 Bits Output Range 0 11 V ACCURACY Total Unadjusted Error (TUE) −0.2 +0.2 %FSR TUE at 25°C −0.15 +0.15 %FSR Integral Nonlinearity (INL) −2 +2 LSB Differential Nonlinearity (DNL) −1 +1 LSB Guaranteed monotonic Offset Error −5.5 +5.5 mV Offset Error at 25°C −3.0 +3.0 mV Gain Error −0.2 +0.2 %FSR Gain Error 25°C −0.18 +0.18 %FSR OUTPUT CHARACTERISTICS Load 500 100k Ω Headroom (500 Ω Load) 4.1 V Minimum voltage difference required between AVDD and the input/output positive (I/OP_x where x is the channel number) screw terminal to provide 11 V across a 500 Ω load Short-Circuit Current (Sourcing) 24.5 29 32.5 mA Per channel, lower limit bit = 0 (default) 5.5 7 9 mA Per channel, lower limit bit = 1 Short-Circuit Current (Sinking) 3.0 3.7 4.5 mA Maximum Capacitive Load 14 nF System capacitance on the I/OP_x screw terminal including the recommended 10 nF; external compensation capacitor (CCOMP) not connected 2 μF External CCOMP = 200 pF connected DC Output Impedance 0.12 Ω DC Power Supply Rejection Ratio (PSRR) 80 dB DYNAMIC PERFORMANCE Output Voltage Settling Time 50 μs 10 V step (0.5 V to 10.5 V or 10.5 V to 0.5 V) to ±0.05 %FSR; CLOAD = 14 nF, no CCOMP connected Noise (External Reference) Measured at the I/OP_x screw terminal, 2.5 V output Output Noise 0.07 LSB p-p 0.1 Hz to 10 Hz bandwidth Output Noise Spectral Density 320 nV/√Hz Measured at 1 kHz AC PSRR 65 dB 200 mV at 1 kHz sine wave superimposed on the AVDD supply Rev. 0 | Page 5 of 70 Document Outline Features Applications General Description Companion Products Product Highlights Revision History Functional Block Diagram Specifications Voltage Output Current Output Voltage Input Current Input Externally Powered and Current Input Externally Powered with HART Current Input Loop Powered Resistance Measurement Digital Input Logic Digital Input Loop Powered ADC Specifications General Specifications Timing Characteristics SPI Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Voltage Output Current Output Digital Input Resistance Measurement Reference ADC Supplies Theory of Operation Robust Architecture Serial Interface DAC Architecture ADC Overview Reference Reference Noise Charge Pump Power-On State of the AD74413R Device Functions High Impedance Interpreting ADC Data Voltage Output Mode Voltage Output Short-Circuit Protection Interpreting ADC Data Current Output Mode Current Output Open Circuit Detection Interpreting ADC Data HART Compatibility Voltage Input Mode Selectable 200 kΩ to GND Interpreting ADC Data Thermocouple Measurement Current Input, Externally Powered Mode Short-Circuit Protection Interpreting ADC Data Current Input, Externally Powered with HART Compatibility Mode Current Input, Loop Powered Mode Short-Circuit Protection Interpreting ADC Data Current Input, Loop Powered with HART Compatibility Mode Resistance Measurement (External 2-Wire RTD) Interpreting ADC Data Digital Input Logic Interpreting ADC Data Digital Input Threshold Setting Digital Input Current Sink Debounce Function Debounce Mode 0 (Default) Debounce Mode 1 Digital Input Inverter Digital Input Counter Digital Input, Loop Powered Mode Interpreting ADC Data Getting Started Using Channel Functions Switching Channel Functions ADC Functionality ADC Conversion Rates ADC_RDYb Functionality ADC Output Data Format ADC Noise Diagnostics DACs LDAC Function Clear Code Function Digital Linear Slew Rate Control HART Compliant Slew Driving Inductive Loads Reset Function Thermal Alert and Thermal Reset Faults and Alerts Channel Faults Power Supply Monitors GPO_x Pins SPI Interface and Diagnostics SPI CRC SPI Interface SCLK Count Feature Readback Mode Streaming Mode Auto Readback Board Design and Layout Considerations Applications Information Register Map NOP Register Function Setup Register per Channel ADC Configuration Register per Channel Digital Input Configuration Register per Channel GPO Parallel Data Register GPO Configuration Register per Channel Output Configuration Register per Channel DAC Code Register per Channel DAC Clear Code Register per Channel DAC Active Code Register per Channel Digital Input Threshold Register ADC Conversion Control Register Diagnostics Select Register Digital Output Level Register ADC Conversion Results Register per Channel Diagnostic Results Registers per Diagnostic Channel Alert Status Register Live Status Register Alert Mask Register Debounced DIN Count Register per Channel Readback Select Register Thermal Reset Enable Register Command Register Scratch or Spare Register Silicon Revision Register Outline Dimensions Ordering Guide