Datasheet LTC3722-1, LTC3722-2 (Analog Devices) - 7
| Fabricante | Analog Devices |
| Descripción | Synchronous Dual Mode Phase Modulated Full Bridge Controllers |
| Páginas / Página | 28 / 7 — PIN FUNCTIONS (LTC3722-1/LTC3722-2). SYNC (Pin 1/Pin 1):. SBUS (Pin … |
| Revisión | C |
| Formato / tamaño de archivo | PDF / 607 Kb |
| Idioma del documento | Inglés |
PIN FUNCTIONS (LTC3722-1/LTC3722-2). SYNC (Pin 1/Pin 1):. SBUS (Pin 10/Pin 10):. DPRG (Pin 2/Pin 5):. ADLY (Pin 11/Pin 11):
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LTC3722-1/LTC3722-2
PIN FUNCTIONS (LTC3722-1/LTC3722-2) SYNC (Pin 1/Pin 1):
Synchronization Input/Output for the
SBUS (Pin 10/Pin 10):
Line Voltage Sense Input. SBUS is Oscillator. The input threshold for SYNC is approximately connected to the main DC voltage feed by a resistive volt- 1.9V, making it compatible with both CMOS and TTL logic. age divider when using adaptive ZVS control. The voltage Terminate SYNC with a 5.1k resistor to GND. divider is designed to produce 1.5V on SBUS at nominal
DPRG (Pin 2/Pin 5):
Programming Input for Default Zero VIN. If SBUS is tied to VREF , the LTC3722-1/LTC3722-2 is Voltage Transition (ZVS) Delay. Connect a resistor from configured for fixed mode ZVS control. DPRG to VREF to set the maximum turn on delay for outputs
ADLY (Pin 11/Pin 11):
Active Leg Delay Circuit Input. ADLY A, B, C, D. The nominal voltage on DPRG is 2V. is connected through a voltage divider to the right leg of
RAMP (NA/Pin 2):
Input to Phase Modulator Comparator the bridge in adaptive ZVS mode. In fixed ZVS mode, a for LTC3722-2 only. The voltage on RAMP is internally voltage between 0V and 2.5V on ADLY, programs a fixed level shifted by 650mV. ZVS delay time for the active leg transition.
CS (Pin 3/Pin 3):
Input to Phase Modulator for the
UVLO (Pin 12/Pin 12):
Input to Program System Turn- LTC3722-1. Input to pulse-by-pulse and overload current On and Turn-Off Voltages. The nominal threshold of the limit comparators, output of slope compensation circuitry. UVLO comparator is 5V. UVLO is connected to the main The pulse by pulse comparator has a nominal 300mV DC system feed through a resistor divider. When the threshold, while the overload comparator has a nominal UVLO threshold is exceeded, the LTC3722-1/LTC3722-2 650mV threshold. commences a soft-start cycle and a 10µA (nominal) cur- rent is fed out of UVLO to program the desired amount of
COMP (Pin 4/Pin 4):
Error Amplifier Output, Inverting system hysteresis. The hysteresis level can be adjusted Input to Phase Modulator. by changing the resistance of the divider.
RLEB (Pin 5/NA):
Timing Resistor for Leading Edge Blank-
SPRG (Pin 13/Pin 13):
A resistor is connected between ing. Use a 10k to 100k resistor to program from 40ns to SPRG and GND to set the turn-off delay for the synchronous 310ns of leading edge blanking of the current sense signal rectifier driver outputs (OUTE and OUTF). The nominal on CS for the LTC3722-1. A ±1% tolerance resistor is voltage on SPRG is 2V. recommended. The LTC3722-2 has a fixed blanking time of approximately 80ns.
VREF (Pin 14/Pin 14):
Output of the 5V Reference. VREF is capable of supplying up to 18mA to external circuitry.
FB (Pin 6/Pin 6):
Error Amplifier Inverting Input. This is VREF should be decoupled to GND with a 1µF ceramic the voltage feedback input for the LTC3722. The nominal capacitor. regulation voltage at FB is 1.204V.
OUTF (Pin 15/Pin 15):
50mA Driver for Synchronous
SS (Pin 7/Pin 7):
Soft-Start/Restart Delay Circuitry Timing Rectifier Associated with OUTB and OUTC. Capacitor. A capacitor from SS to GND provides a controlled ramp of the current command (LTC3722-1), or duty cycle
OUTE (Pin 16/Pin 16):
50mA Driver for Synchronous (LTC3722-2). During overload conditions SS is discharged Rectifier Associated with OUTA and OUTD. to ground initiating a soft-start cycle.
OUTD (Pin 17/Pin 17):
50mA Driver for Low Side of the
NC (Pin 8/Pin 8):
No Connection. Tie this pin to GND. Full Bridge Active Leg.
PDLY (Pin 9/Pin 9):
Passive Leg Delay Circuit Input. PDLY
VCC (Pin 18/Pin 18):
Supply Voltage Input to the is connected through a voltage divider to the left leg of LTC3722-1/LTC3722-2 and 10.25V Shunt Regulator. the bridge in adaptive ZVS mode. In fixed ZVS mode, a The chip is enabled after VCC has risen high enough to voltage between 0V and 2.5V on PDLY, programs a fixed allow the VCC shunt regulator to conduct current and the ZVS delay time for the passive leg transition. UVLO comparator threshold is exceeded. Once the VCC shunt regulator has turned on, VCC can drop to as low as 6V (typ) and maintain operation. Rev C For more information www.analog.com 7 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Timing Diagram Operation Revision History Typical application Related Parts
PIN FUNCTIONS (LTC3722-1/LTC3722-2) SYNC (Pin 1/Pin 1):
Synchronization Input/Output for the
SBUS (Pin 10/Pin 10):
Line Voltage Sense Input. SBUS is Oscillator. The input threshold for SYNC is approximately connected to the main DC voltage feed by a resistive volt- 1.9V, making it compatible with both CMOS and TTL logic. age divider when using adaptive ZVS control. The voltage Terminate SYNC with a 5.1k resistor to GND. divider is designed to produce 1.5V on SBUS at nominal
DPRG (Pin 2/Pin 5):
Programming Input for Default Zero VIN. If SBUS is tied to VREF , the LTC3722-1/LTC3722-2 is Voltage Transition (ZVS) Delay. Connect a resistor from configured for fixed mode ZVS control. DPRG to VREF to set the maximum turn on delay for outputs
ADLY (Pin 11/Pin 11):
Active Leg Delay Circuit Input. ADLY A, B, C, D. The nominal voltage on DPRG is 2V. is connected through a voltage divider to the right leg of
RAMP (NA/Pin 2):
Input to Phase Modulator Comparator the bridge in adaptive ZVS mode. In fixed ZVS mode, a for LTC3722-2 only. The voltage on RAMP is internally voltage between 0V and 2.5V on ADLY, programs a fixed level shifted by 650mV. ZVS delay time for the active leg transition.
CS (Pin 3/Pin 3):
Input to Phase Modulator for the
UVLO (Pin 12/Pin 12):
Input to Program System Turn- LTC3722-1. Input to pulse-by-pulse and overload current On and Turn-Off Voltages. The nominal threshold of the limit comparators, output of slope compensation circuitry. UVLO comparator is 5V. UVLO is connected to the main The pulse by pulse comparator has a nominal 300mV DC system feed through a resistor divider. When the threshold, while the overload comparator has a nominal UVLO threshold is exceeded, the LTC3722-1/LTC3722-2 650mV threshold. commences a soft-start cycle and a 10µA (nominal) cur- rent is fed out of UVLO to program the desired amount of
COMP (Pin 4/Pin 4):
Error Amplifier Output, Inverting system hysteresis. The hysteresis level can be adjusted Input to Phase Modulator. by changing the resistance of the divider.
RLEB (Pin 5/NA):
Timing Resistor for Leading Edge Blank-
SPRG (Pin 13/Pin 13):
A resistor is connected between ing. Use a 10k to 100k resistor to program from 40ns to SPRG and GND to set the turn-off delay for the synchronous 310ns of leading edge blanking of the current sense signal rectifier driver outputs (OUTE and OUTF). The nominal on CS for the LTC3722-1. A ±1% tolerance resistor is voltage on SPRG is 2V. recommended. The LTC3722-2 has a fixed blanking time of approximately 80ns.
VREF (Pin 14/Pin 14):
Output of the 5V Reference. VREF is capable of supplying up to 18mA to external circuitry.
FB (Pin 6/Pin 6):
Error Amplifier Inverting Input. This is VREF should be decoupled to GND with a 1µF ceramic the voltage feedback input for the LTC3722. The nominal capacitor. regulation voltage at FB is 1.204V.
OUTF (Pin 15/Pin 15):
50mA Driver for Synchronous
SS (Pin 7/Pin 7):
Soft-Start/Restart Delay Circuitry Timing Rectifier Associated with OUTB and OUTC. Capacitor. A capacitor from SS to GND provides a controlled ramp of the current command (LTC3722-1), or duty cycle
OUTE (Pin 16/Pin 16):
50mA Driver for Synchronous (LTC3722-2). During overload conditions SS is discharged Rectifier Associated with OUTA and OUTD. to ground initiating a soft-start cycle.
OUTD (Pin 17/Pin 17):
50mA Driver for Low Side of the
NC (Pin 8/Pin 8):
No Connection. Tie this pin to GND. Full Bridge Active Leg.
PDLY (Pin 9/Pin 9):
Passive Leg Delay Circuit Input. PDLY
VCC (Pin 18/Pin 18):
Supply Voltage Input to the is connected through a voltage divider to the left leg of LTC3722-1/LTC3722-2 and 10.25V Shunt Regulator. the bridge in adaptive ZVS mode. In fixed ZVS mode, a The chip is enabled after VCC has risen high enough to voltage between 0V and 2.5V on PDLY, programs a fixed allow the VCC shunt regulator to conduct current and the ZVS delay time for the passive leg transition. UVLO comparator threshold is exceeded. Once the VCC shunt regulator has turned on, VCC can drop to as low as 6V (typ) and maintain operation. Rev C For more information www.analog.com 7 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Timing Diagram Operation Revision History Typical application Related Parts