Datasheet ADP1074 (Analog Devices)

Isolated, Synchronous Forward Controller with Active Clamp and
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Coupler Data Sheet ADP1074 FEATURES Remote (secondary side) shutdown/reset function Current mode controller for active clamp forward topology Safety and regulatory approvals (p ending) Integrated 5 kV (wide body SOIC package) or 3.0 kV (LGA UL recognition package) rated dielectric isolation voltage with Analog 5000 V rms for 1 minute per UL 1577 (for wide body Devices, Inc., patented i Coupler technology SOIC package) Wide voltage supply range 3000 V rms for 1 minute per UL 1577 (for LGA package) Primary VIN: up to 60 V CSA component acceptance notice 5A Secondary VDD2: up to 36 V VDE certificate of conformity Integrated 1 A primary side MOSFET driver for power switch DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 and active clamp reset switch VIORM = 849 V peak (for wide body SOIC package) Integrated 1 A secondary side MOSFET drivers for VIORM = 560 V peak (for LGA package) synchronous rectification CQC certification per GB4943.1-2011 Integrated error amplifier and <1% accurate reference voltage Available in 24-lead SOIC_W package and 24-terminal LGA Programmable slope compensation package Programmable frequency range: 50 kHz to 600 kHz typical AEC-Q100 Qualified for Automotive Applications Frequency synchronization APPLICATIONS Programmable maximum duty cycle limit Programmable soft start Isolated dc-to-dc power conversion Smooth soft start from precharged load Intermediate bus voltage generation Programmable dead time Telecom, industrial Power saving light load mode using MODE pin Base station and antenna RF power Protection features such as short circuit, output overvoltage, Small cell and overtemperature protection PoE powered device Cycle-by-cycle input overcurrent protection Enterprise switches/routers Precision enable UVLO with hysteresis Core/edge/metro/optical routing PGOOD pin for system flagging Power modules Tracking function from secondary side SIMPLIFIED BLOCK DIAGRAM ACTIVE CLAMP SYNCHRONOUS INPUT 12V FORWARD DC/8A RECTIFIER BIAS WDG OPTIONAL START-UP CIRCUITRY ADP1074
001 15627- Figure 1.
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Document Outline FEATURES APPLICATIONS SIMPLIFIED BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS INSULATION AND SAFETY RELATED SPECIFICATIONS REGULATORY INFORMATION DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION DETAILED BLOCK DIAGRAM PRIMARY SIDE SUPPLY, INPUT VOLTAGE, AND LDO SECONDARY SIDE SUPPLY AND LDO PRECISION ENABLE SOFT START PROCEDURE OUTPUT VOLTAGE SENSING AND FEEDBACK LOOP COMPENSATION AND STEADY STATE OPERATION SLOPE COMPENSATION INPUT/OUTPUT CURRENT-LIMIT PROTECTION TEMPERATURE SENSING FREQUENCY SETTING (RT PIN) MAXIMUM DUTY CYCLE FREQUENCY SYNCHRONIZATION SYNCHRONOUS RECTIFIER (SR) DRIVERS OUTPUT OVERVOLTAGE PROTECTION (OVP) ACTIVE CLAMP (PGATE) LEADING EDGE BLANKING GATE DELAY AND SR DEAD TIME LIGHT LOAD MODE (LLM) AND SR PHASE IN EXTERNAL START-UP CIRCUIT SOFT STOP POWER GOOD OCP/FEEDBACK RECOVERY OUTPUT VOLTAGE TRACKING REMOTE SYSTEM RESET OCP COUNTER INSULATION LIFETIME LAYOUT GUIDELINES TYPICAL APPLICATION CIRCUITS OUTLINE DIMENSIONS ORDERING GUIDE NOTES