Datasheet ADE7816 (Analog Devices) - 44

ADE7816 Data Sheet Default Bits Bit Name Value Description
[5:3] PGA2[2:0] 0x000 Voltage channel gain selection. 000: gain = 1 001: gain = 2. 010: gain = 4. 011: gain = 8. 100: gain = 16. 101, 110, 111: reserved. [2:0] PGA1[2:0] 0x000 Gain selection for the A, B, and C current channels. 000: gain = 1. 001: gain = 2. 010: gain = 4. 011: gain = 8. 100: gain = 16. 101, 110, 111: reserved.
Table 23. CHSIGN Register (Address 0xE617) Default Bits Bit Name Value Description
[15:7] Reserved 0x0000000 These bits should be ignored. 6 VAR3SIGN 0x0 0: the reactive power on the C or F channel is positive. 1: the reactive power on the C or F channel is negative. 5 VAR2SIGN 0x0 0: the reactive power on the B or E channel is positive. 1: the reactive power on the B or E channel is negative. 4 VAR1SIGN 0x0 0: the reactive power on the A or D channel is positive. 1: the reactive power on the A or D channel is negative. 3 Reserved 0x0 This bit should be ignored. 2 W3SIGN 0x0 0: the active power on the C or F channel is positive. 1: the active power on the C or F channel is negative. 1 W2SIGN 0x0 0: the active power on the B or E channel is positive. 1: the active power on the B or E channel is negative. 0 W1SIGN 0x0 0: the active power on the A or D channel is positive. 1: the active power on the A or D channel is negative.
Table 24. CONFIG Register (Address 0xE618) Default Bits Bit Name Value Description
[15:8] Reserved 0x0 These bits should be ignored. 7 SWRST 0x0 Initiates a software reset. 6 HSDCEN 0x0 Enables the HSDC serial port. [5:1] Reserved 0x0 These bits should be ignored. 0 INTEN 0x0 Enables the digital integrator.
Table 25. MMODE Register (Address 0xE700) Default Bits Bit Name Value Description
[7:5] Reserved 0x000 These bits should be ignored. 4 PEAKSEL2 0x1 The C or F current channel is selected for peak detection. 3 PEAKSEL1 0x1 The B or E current channel is selected for peak detection. 2 PEAKSEL0 0x1 The A or D current channel is selected for peak detection. [1:0] Reserved 0x00 These bits should be ignored. Rev. B | Page 44 of 48 Document Outline Features General Description Functional Block Diagram Revision History Specifications Timing Characteristics I2C-Compatible Interface Timing SPI Interface Timing HSDC Interface Timing Load Circuit for All Timing Specifications Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Test Circuit Terminology Quick Start Inputs Power and Ground VDD and AGND, DGND Reference Circuit REFIN/OUT Reset Hardware Reset Software Reset Functionality CLKIN and CLKOUT Analog Inputs Input Pins PGA Gain Digital Integrator Antialiasing Filters Energy Measurements Starting and Stopping the DSP Active Energy Measurement Definition of Active Power and Active Energy Active Energy Registers Active Energy Threshold Energy Accumulation and Register Roll-Over Reactive Energy Measurement Definition of Reactive Power and Reactive Energy Reactive Energy Registers Reactive Energy Threshold Reactive Energy Accumulation and Register Roll-Over Line Cycle Accumulation Mode Root Mean Square Measurement No Load Detection Setting the No Load Thresholds No Load Interrupt Energy Calibration Channel Matching Energy Gain Calibration Energy Offset Calibration Energy Phase Calibration RMS Offset Calibration Power Quality Features Selecting a Current Channel Group Instantaneous Waveforms Zero-Crossing Detection Zero-Crossing Detection Zero-Crossing Timeout Peak Detection Setting the PEAKCYC Register Overcurrent and Overvoltage Detection Setting the OVLVL and OILVL Registers Overvoltage and Overcurrent Interrupts Indication of Power Direction Angle Measurements Period Measurement Voltage Sag Detection Setting the SAGCYC Register Setting the SAGLVL Register Voltage Sag Interrupt Checksum Layout Guidelines Crystal Circuit Outputs Interrupts Communication Serial Interface Selection I2C-Compatible Interface I2C Write Operation I2C Read Operation SPI-Compatible Interface SPI Read Operation SPI Write Operation HSDC Interface Registers Register Protection Register Format Register Maps Register Descriptions Interrupt Enable and Interrupt Status Registers Outline Dimensions Ordering Guide