Datasheet AD2420(W), AD2426(W), AD2427(W), AD2428(W), AD2429(W) (Analog Devices) - 6

link to page 12
AD2420(W) /AD2426(W) /AD2427(W) /AD2428(W) / AD2429(W) I2S Reduced Rate
used to customize handshaking among numerous nodes in a system to coordinate system events, such as synchronizing Slave transceivers can run the I2S/TDM/PDM interface at a audio. reduced rate frequency, with respect to the superframe rate. The reduced rate frequency is derived by dividing the superframe
DATA SLOT EXCHANGE BETWEEN SLAVES
rate from a programmable set of values. Different slave nodes can be configured to run at different reduced I2S/TDM rates. Using the DTX0 and DTX1 pins, slave transceivers can selec- tively output upstream or downstream data that originates from The transceiver provides an option for a processor to track the other nodes without the need for data slots to be routed through full rate audio frame, which contains new reduced rate samples. the master node. Receive data channels can be skipped based on The IO7 pin can be used as a strobe, and the direction can be a programmable offset, when the data is presented as upstream configured as an input or output. or downstream slots to the A2B bus.
PULSE DENSITY MODULATION (PDM) INTERFACE CLOCK SUSTAIN STATE
The PDM block on the transceiver converts a PDM input In the clock sustain state, audio signals of locally powered slave stream into pulse code modulated (PCM) data to be sent over nodes are attenuated in the event of lost bus communication. the A2B bus and/or out to the local node through the I2S/TDM When the bus loses communication and a reliable clock cannot port. It supports high dynamic range microphones with high be recovered by the slave node, the slave node transceiver enters signal-to-noise ratio (SNR) and extended maximum sound the sustain state and, if enabled, signals this event to a GPIO pin. pressure level. The PDM interface supports 12 kHz and 24 kHz frame rates in addition to a 48 kHz frame rate and can be used In the clock sustain state, the phase-locked loop (PLL) of the on both master and slave transceivers. slave node transceiver continues to run for 1024 SYNC periods, while attenuating the I2S DTX0 to DTX1 data from the current Even lower PDM sampling rates (for example, down to 375 Hz) value to 0. After the 1024 SYNC periods, the slave node trans- are possible in combination with the reduced rate feature of the ceiver resets and reenters the power-up state. transceiver. The cutoff frequency of the high-pass filter in the transceiver PDM block is fixed to 1 Hz.
PROGRAMMABLE SETTINGS TO OPTIMIZE EMC
BCLK can be used to clock PDM microphones on a slave, but if
PERFORMANCE
PDMCLK/IO7 is used instead, the BCLK frequency can be set to The following programmable features can be used to improve a different frequency using the I2S/TDM registers. In this case, electromagnetic compatibility (EMC) performance. PDMCLK/IO7 is used as the PDM clock (PDMCLK) to capture PDM input on DRX0/DRX1. The clock rate from PDMCLK is
Programmable LVDS Transmit Levels
64× the SYNC frequency. The low voltage differential signal (LVDS) transmitter can be set On a master node, BCLK is always an input, so the clock to to transmit the signal at high, medium, or low levels. Higher PDM microphones that are attached to a master typically comes transmit levels yield greater immunity to EMI, whereas lower from PDMCLK/IO7. It is possible to use BCLK to drive the transmit levels can reduce emissions from the twisted-pair PDM clock inputs on a master node, but this restricts the possi- cables that link A2B bus nodes together. The improved LVDS ble TDM settings because BCLK is required to fall within the receiver (compared to other members of the AD242xW family) fBCLK specification in Table 4. maintains robust operation when transmit levels are lowered. BCLK and PDMCLK/IO7 can also be used concurrently to
Spread-Spectrum Clocking
clock PDM microphones at the same frequency and phase alignment, but with opposite polarity. Additionally, a register Spread-spectrum clocking can be used to reduce narrow-band setting selects whether rising edge data or falling edge data is emissions on a printed circuit board (PCB). Spread-spectrum sampled first. clocking is disabled on the transceiver by default, but spread- spectrum clocking for all internal clocks can be enabled during
GPIO OVER DISTANCE
discovery by a register write. The transceiver supports general-purpose input/output (GPIO) If spread-spectrum clocking support is enabled for the internal between multiple nodes without host intervention after initial clocks, spread-spectrum clocking can also be enabled for both programming. The host is required only for initial setup of the the I2S interface and the programmed CLKOUTs. Enabling GPIO bus ports. I/O pins of different nodes can be logically OR spread-spectrum clocking for internal clocks, CLKOUTs, and or AND gate combined. the I2S interface may reduce narrow-band emissions by several dB on a particular node. When spread-spectrum clocking is
MAILBOXES
enabled on a clock output, the time interval error (TIE) jitter on The transceiver supports interrupt driven, bidirectional mes- that clock increases. sage exchange between I2C master devices (microcontrollers) at
Unique ID
different slave nodes and the host connected to the master node transceiver in two dedicated mailboxes. The mailboxes can be Each transceiver contains a unique ID, which can be read from registers using software. If a read of the unique ID fails, an inter- rupt can be generated. Rev. B | Page 6 of 38 | January 2020 Document Outline Automotive Audio Bus A2B Transceiver A2B Bus Features A2B Transceiver Features Applications Table of Contents Revision History General Description A2B Bus Details I2C Interface I2S/TDM Interface I2S Reduced Rate Pulse Density Modulation (PDM) Interface GPIO Over Distance Mailboxes Data Slot Exchange Between Slaves Clock Sustain State Programmable Settings to Optimize EMC Performance Programmable LVDS Transmit Levels Spread-Spectrum Clocking Unique ID Support for Crossover or Straight Through Cabling Data Only and Power Only Bus Operation Specifications Operating Conditions Electrical Characteristics Power Supply Rejection Ratio (PSRR) Timing Specifications Power-Up Sequencing Restrictions A2B Bus System Specification RMS Time Interval Error (TIE) Jitter PDM Typical Performance Characteristics Absolute Maximum Ratings Thermal Characteristics ESD Caution Test Circuits and Switching Characteristics Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Capacitive Loading Pin Configuration and Function Descriptions Power Analysis Current Flow Constant Current PLL Supply Current VIN Quiescent Current IOVDD Current Peripheral Supply Current Digital Logic Supply Current A2B Bus TX/RX Current LVDS Transmitter and Receiver Supply Currents Downstream/Upstream Activity Level LVDS Transmitter and Receiver Idle Current VREG1 and VREG2 Output Currents Current at VIN (IVIN) Power Dissipation Resistance Between Nodes Voltage Regulator Current in Master Node or Local Powered Slave Node Power Dissipation of A2B Bus Power Analysis of Bus Powered System Supply Voltage Reducing Power Consumption Power-Down Mode Standby Mode Control Mode Thermal Power Designer Reference VSENSE and Considerations for Diodes Optional Add On Circuits Layout Guidelines Outline Dimensions Automotive Products Ordering Guide