Datasheet VSC7424-02, VSC7425-02, VSC7426-02, VSC7427-02 (Microchip)

VSC7424-02, VSC7425-02, VSC7426-02, and VSC7427-02 Datasheet Family of Managed Gigabit Ethernet Switches
Document Outline 1 Revision History 1.1 Revision 4.2 1.2 Revision 4.1 1.3 Revision 4.0 1.4 Revision 2.0 2 Introduction 2.1 Register Notation 2.2 Standard References 2.3 Terms and Abbreviations 3 Product Overview 3.1 General Features 3.1.1 Layer-2 Switching 3.1.2 Multicast 3.1.3 Quality of Service 3.1.4 Security 3.1.5 Management 3.2 Applications 3.3 Related Products 3.4 Functional Overview 3.4.1 Frame Arrival 3.4.2 Basic and Advanced Frame Classification 3.4.3 VCAP-II Vitesse Content Aware Processor 3.4.4 Policing 3.4.5 Layer-2 Forwarding 3.4.6 Shared Queue System and Egress Scheduler 3.4.7 Rewriter and Frame Departure 3.4.8 CPU Port Module 3.4.9 CPU System and Interfaces 4 Functional Descriptions 4.1 Port Modules 4.1.1 Port Module Numbering and Macro Connections 4.1.2 MAC 4.1.3 PCS 4.2 SERDES1G 4.2.1 SERDES1G Basic Configuration 4.2.2 SERDES1G Loopback Modes 4.2.3 SERDES1G Deserializer Configuration 4.2.4 SERDES1G Serializer Configuration 4.2.5 SERDES1G Input Buffer Configuration 4.2.6 SERDES1G Output Buffer Configuration 4.2.7 SERDES1G Clock and Data Recovery (CDR) in 100BASE-FX 4.2.8 SERDES1G Energy Efficient Ethernet 4.2.9 SERDES1G Data Inversion 4.3 SERDES6G 4.3.1 SERDES6G Basic Configuration 4.3.2 SERDES6G Loopback Modes 4.3.3 SERDES6G Deserializer Configuration 4.3.4 SERDES6G Serializer Configuration 4.3.5 SERDES6G Input Buffer Configuration 4.3.6 SERDES6G Output Buffer Configuration 4.3.7 SERDES6G Clock and Data Recovery (CDR) in 100BASE-FX 4.3.8 SERDES6G Energy Efficient Ethernet 4.3.9 SERDES6G Data Inversion 4.3.10 SERDES6G Signal Detection Enhancements 4.3.11 SERDES6G High-Speed I/O Configuration Bus 4.4 Copper Transceivers 4.4.1 Register Access 4.4.2 Cat5 Twisted Pair Media Interface 4.4.3 LED Interface 4.4.4 Ethernet Inline Powered Devices 4.4.5 IEEE 802.3af PoE Support 4.4.6 ActiPHY™ Power Management 4.4.7 Testing Features 4.4.8 VeriPHY™ Cable Diagnostics 4.5 Statistics 4.6 Classifier 4.6.1 General Data Extraction Setup 4.6.2 Frame Acceptance Filtering 4.6.3 QoS, DP, and DSCP Classification 4.6.4 VLAN Classification 4.6.5 Link Aggregation Code Generation 4.6.6 CPU Forwarding Determination 4.7 VCAP-II 4.7.1 Port Configuration 4.7.2 VCAP IS1 4.7.3 VCAP IS2 4.7.4 VCAP ES0 4.7.5 Range Checkers 4.7.6 VCAP-II Configuration 4.7.7 Advanced VCAP Operations 4.8 Analyzer 4.8.1 MAC Table 4.8.2 VLAN Table 4.8.3 Forwarding Engine 4.8.4 Analyzer Monitoring 4.9 Policers and Ingress Shapers 4.9.1 Policers 4.9.2 Ingress Shapers 4.10 Shared Queue System 4.10.1 Buffer Management 4.10.2 Frame Reference Management 4.10.3 Resource Depletion Condition 4.10.4 Configuration Example 4.10.5 Watermark Programming and Consumption Monitoring 4.10.6 Advanced Resource Management 4.10.7 Ingress Pause Request Generation 4.10.8 Tail Dropping 4.10.9 Test Utilities 4.10.10 Energy Efficient Ethernet 4.11 Scheduler and Shaper 4.11.1 Egress Shapers 4.11.2 Deficit Weighted Round Robin 4.11.3 Shaping and DWRR Scheduling Examples 4.12 Rewriter 4.12.1 VLAN Editing 4.12.2 DSCP Remarking 4.12.3 FCS Updating 4.12.4 CPU Extraction Header Insertion 4.13 CPU Port Module 4.13.1 Frame Extraction 4.13.2 Frame Injection 4.13.3 Network Processor Interface (NPI) 4.14 Hardware Timestamping for AVB 4.14.1 Timestamp Classification 4.14.2 One-Second Timer 4.14.3 Delay Timer 4.14.4 Time of Day Counter 4.15 Clocking and Reset 5 VCore-III System and CPU Interface 5.1 VCore-III Configurations 5.2 Clocking and Reset 5.2.1 Watchdog Timer 5.3 Shared Bus 5.3.1 Shared Bus Arbitration 5.3.2 SI Memory Region 5.3.3 PI Memory Region 5.3.4 DDR2 Memory Region 5.3.5 Switch Core Registers Memory Region 5.3.6 VCore-III Registers Memory Region 5.4 VCore-III CPU 5.4.1 Big Endian Support 5.4.2 Software Debug and Development 5.5 Manual Frame Injection and Extraction 5.5.1 Manual Frame Extraction 5.5.2 Manual Frame Injection 5.5.3 Frame Interrupts 5.6 Frame DMA 5.6.1 DMA Control Block Structures 5.6.2 Extraction 5.6.3 Injection 5.6.4 Frame DMA Interrupt 5.7 External CPU Support 5.7.1 Register Access and Multimaster Systems 5.7.2 Serial Interface in Slave Mode 5.7.3 Parallel Interface in Slave Mode 5.7.4 MIIM Interface in Slave Mode 5.7.5 Access to the VCore-III Shared Bus 5.7.6 Mailbox and Semaphores 5.8 VCore-III System Peripherals 5.8.1 Timers 5.8.2 UART 5.8.3 Two-Wire Serial Interface 5.8.4 MII Management Controller 5.8.5 GPIO Controller 5.8.6 Serial GPIO Controller 5.8.7 FAN Controller 5.8.8 Interrupt Controller 6 Features 6.1 Port Mapping 6.1.1 VSC7424-02 Port Mapping 6.1.2 VSC7425-02 Port Mapping 6.1.3 VSC7426-02 Port Mapping 6.1.4 VSC7427-02 Port Mapping 6.2 Switch Control 6.2.1 Switch Initialization 6.3 Port Module Control 6.3.1 MAC Configuration Port Mode Control 6.3.2 SerDes Configuration Port Mode Control 6.3.3 Port Reset Procedure 6.3.4 Port Counters 6.4 Layer-2 Switch 6.4.1 Basic Switching 6.4.2 Standard VLAN Operation 6.4.3 Provider Bridges and Q-in-Q Operation 6.4.4 Private VLANs 6.4.5 Asymmetric VLANs 6.4.6 Spanning Tree Protocols 6.4.7 IEEE 802.1X: Network Access Control 6.4.8 Link Aggregation 6.4.9 Simple Network Management Protocol (SNMP) 6.4.10 Mirroring 6.5 IGMP and MLD Snooping 6.5.1 IGMP and MLD Snooping Configuration 6.5.2 IP Multicast Forwarding Configuration 6.6 Quality of Service (QoS) 6.6.1 Basic QoS Configuration 6.6.2 IPv4 and IPv6 DSCP Remarking 6.6.3 Voice over IP (VoIP) 6.7 VCAP Applications 6.7.1 Notation for Control Lists Entries 6.7.2 Ingress Control Lists 6.7.3 Access Control Lists 6.7.4 Source IP Filter (SIP Filter) 6.7.5 DHCP Application 6.7.6 ARP Filtering 6.7.7 Ping Policing 6.7.8 TCP SYN Policing 6.8 CPU Extraction and Injection 6.8.1 Forwarding to CPU 6.8.2 Frame Extraction 6.8.3 Frame Injection 6.8.4 Frame Extraction and Injection Using An External CPU 6.9 Audio Video Bridging 6.10 Energy Efficient Ethernet 7 Registers 7.1 Targets and Base Addresses 7.2 DEVCPU_ORG 7.2.1 DEVCPU_ORG:ORG 7.3 SYS 7.3.1 SYS:SYSTEM 7.3.2 SYS:SCH 7.3.3 SYS:SCH_LB 7.3.4 SYS:RES_CTRL 7.3.5 SYS:PAUSE_CFG 7.3.6 SYS:MMGT 7.3.7 SYS:MISC 7.3.8 SYS:STAT 7.3.9 SYS:PTP 7.3.10 SYS:POL 7.3.11 SYS:POL_MISC 7.3.12 SYS:ISHP 7.4 ANA 7.4.1 ANA:ANA 7.4.2 ANA:ANA_TABLES 7.4.3 ANA:PORT 7.4.4 ANA:COMMON 7.5 REW 7.5.1 REW:PORT 7.5.2 REW:COMMON 7.6 VCAP_CORE 7.6.1 VCAP_CORE:VCAP_CORE_CFG 7.6.2 VCAP_CORE:VCAP_CORE_CACHE 7.6.3 VCAP_CORE:VCAP_CORE_STICKY 7.6.4 VCAP_CORE:VCAP_CONST 7.6.5 VCAP_CORE:TCAM_BIST 7.7 VCAP_CORE 7.7.1 VCAP_CORE:VCAP_CORE_CFG 7.7.2 VCAP_CORE:VCAP_CORE_CACHE 7.7.3 VCAP_CORE:VCAP_CORE_STICKY 7.7.4 VCAP_CORE:VCAP_CONST 7.7.5 VCAP_CORE:TCAM_BIST 7.8 VCAP_CORE 7.8.1 VCAP_CORE:VCAP_CORE_CFG 7.8.2 VCAP_CORE:VCAP_CORE_CACHE 7.8.3 VCAP_CORE:VCAP_CORE_STICKY 7.8.4 VCAP_CORE:VCAP_CONST 7.8.5 VCAP_CORE:TCAM_BIST 7.9 DEVCPU_GCB 7.9.1 DEVCPU_GCB:CHIP_REGS 7.9.2 DEVCPU_GCB:SW_REGS 7.9.3 DEVCPU_GCB:VCORE_ACCESS 7.9.4 DEVCPU_GCB:GPIO 7.9.5 DEVCPU_GCB:DEVCPU_RST_REGS 7.9.6 DEVCPU_GCB:MIIM 7.9.7 DEVCPU_GCB:MIIM_READ_SCAN 7.9.8 DEVCPU_GCB:RAM_STAT 7.9.9 DEVCPU_GCB:MISC 7.9.10 DEVCPU_GCB:SIO_CTRL 7.9.11 DEVCPU_GCB:FAN_CFG 7.9.12 DEVCPU_GCB:FAN_STAT 7.9.13 DEVCPU_GCB:PTP_CFG 7.9.14 DEVCPU_GCB:PTP_STAT 7.9.15 DEVCPU_GCB:PTP_TIMERS 7.9.16 DEVCPU_GCB:MEMITGR 7.10 DEVCPU_QS 7.10.1 DEVCPU_QS:XTR 7.10.2 DEVCPU_QS:INJ 7.11 DEVCPU_PI 7.11.1 DEVCPU_PI:PI 7.12 HSIO 7.12.1 HSIO:PLL5G_CFG 7.12.2 HSIO:PLL5G_STATUS 7.12.3 HSIO:RCOMP_STATUS 7.12.4 HSIO:SERDES1G_ANA_CFG 7.12.5 HSIO:SERDES1G_DIG_CFG 7.12.6 HSIO:SERDES1G_DIG_STATUS 7.12.7 HSIO:MCB_SERDES1G_CFG 7.12.8 HSIO:SERDES6G_ANA_CFG 7.12.9 HSIO:SERDES6G_DIG_CFG 7.12.10 HSIO:MCB_SERDES6G_CFG 7.13 DEV_GMII 7.13.1 DEV_GMII:PORT_MODE 7.13.2 DEV_GMII:MAC_CFG_STATUS 7.14 DEV 7.14.1 DEV:PORT_MODE 7.14.2 DEV:MAC_CFG_STATUS 7.14.3 DEV:PCS1G_CFG_STATUS 7.14.4 DEV:PCS1G_TSTPAT_CFG_STATUS 7.14.5 DEV:PCS_FX100_CONFIGURATION 7.14.6 DEV:PCS_FX100_STATUS 7.15 ICPU_CFG 7.15.1 ICPU_CFG:CPU_SYSTEM_CTRL 7.15.2 ICPU_CFG:PI_MST 7.15.3 ICPU_CFG:SPI_MST 7.15.4 ICPU_CFG:INTR 7.15.5 ICPU_CFG:GPDMA 7.15.6 ICPU_CFG:INJ_FRM_SPC 7.15.7 ICPU_CFG:TIMERS 7.15.8 ICPU_CFG:MEMCTRL 7.15.9 ICPU_CFG:TWI_DELAY 7.16 UART 7.16.1 UART:UART 7.17 TWI 7.17.1 TWI:TWI 7.18 SBA 7.18.1 SBA:SBA 7.19 GPDMA 7.19.1 GPDMA:CH 7.19.2 GPDMA:INTR 7.19.3 GPDMA:MISC 7.20 PHY 7.20.1 PHY:PHY_STD 7.20.2 PHY:PHY_EXT1 7.20.3 PHY:PHY_EXT2 7.20.4 PHY:PHY_GP 7.20.5 PHY:PHY_EEE 8 Electrical Specifications 8.1 DC Characteristics 8.1.1 Internal Pull-Up or Pull-Down Resistors 8.1.2 Reference Clock 8.1.3 DDR2 SDRAM Interface 8.1.4 SGMII DC Definitions and Test Circuits 8.1.5 Enhanced SerDes Interface 8.1.6 SerDes (SGMII) Interface 8.1.7 MIIM, GPIO, SI, JTAG, and Miscellaneous Signals 8.1.8 Thermal Diode 8.2 AC Characteristics 8.2.1 Reference Clock 8.2.2 Reset Timing 8.2.3 DDR2 SDRAM Signal 8.2.4 Enhanced SerDes Interface 8.2.5 SerDes (SGMII) Interface 8.2.6 MII Management 8.2.7 Serial CPU Interface (SI) Master Mode 8.2.8 Serial CPU Interface (SI) for Slave Mode 8.2.9 Parallel Interface (PI) Master Mode 8.2.10 Parallel Interface (PI) Slave Mode 8.2.11 JTAG Interface 8.2.12 Serial Inputs/Outputs 8.2.13 Two-Wire Serial Interface 8.3 Current and Power Consumption 8.3.1 Current Consumption 8.3.2 Power Consumption 8.3.3 Power Supply Sequencing 8.4 Operating Conditions 8.5 Stress Ratings 9 Pin Descriptions for VSC7424-02 9.1 Pin Diagram for VSC7424-02 9.2 Pins by Function for VSC7424-02 9.2.1 Analog Bias Signals 9.2.2 Clock Circuits 9.2.3 DDR2 SDRAM Interface 9.2.4 General-Purpose Inputs and Outputs 9.2.5 JTAG Interface 9.2.6 MII Management Interface 9.2.7 Miscellaneous Signals 9.2.8 Parallel Interface 9.2.9 Power Supplies and Ground 9.2.10 Serial CPU Interface 9.2.11 SerDes Interface 9.2.12 Twisted Pair Interface 9.3 Pins by Number for VSC7424-02 9.4 Pins by Name for VSC7424-02 10 Pin Descriptions for VSC7425-02 10.1 Pin Diagram for VSC7425-02 10.2 Pins by Function for VSC7425-02 10.2.1 Analog Bias Signals 10.2.2 Clock Circuits 10.2.3 DDR2 SDRAM Interface 10.2.4 General-Purpose Inputs and Outputs 10.2.5 JTAG Interface 10.2.6 MII Management Interface 10.2.7 Miscellaneous Signals 10.2.8 Parallel Interface 10.2.9 Power Supplies and Ground 10.2.10 Serial CPU Interface 10.2.11 SerDes Interface 10.2.12 Enhanced SerDes Interface 10.2.13 Twisted Pair Interface 10.3 Pins by Number for VSC7425-02 10.4 Pins by Name for VSC7425-02 11 Pin Descriptions for VSC7426-02 11.1 Pin Diagram for VSC7426-02 11.2 Pins by Function for VSC7426-02 11.2.1 Analog Bias Signals 11.2.2 Clock Circuits 11.2.3 DDR2 SDRAM Interface 11.2.4 General-Purpose Inputs and Outputs 11.2.5 JTAG Interface 11.2.6 MII Management Interface 11.2.7 Miscellaneous Signals 11.2.8 Parallel Interface 11.2.9 Power Supplies and Ground 11.2.10 Serial CPU Interface 11.2.11 Enhanced SerDes Interface 11.2.12 Twisted Pair Interface 11.3 Pins by Number for VSC7426-02 11.4 Pins by Name for VSC7426-02 12 Pin Descriptions for VSC7427-02 12.1 Pin Diagram for VSC7427-02 12.2 Pins by Function for VSC7427-02 12.2.1 Analog Bias Signals 12.2.2 Clock Circuits 12.2.3 DDR2 SDRAM Interface 12.2.4 General-Purpose Inputs and Outputs 12.2.5 JTAG Interface 12.2.6 MII Management Interface 12.2.7 Miscellaneous Signals 12.2.8 Parallel Interface 12.2.9 Power Supplies and Ground 12.2.10 Serial CPU Interface 12.2.11 SerDes Interface 12.2.12 Enhanced SerDes Interface 12.2.13 Twisted Pair Interface 12.3 Pins by Number for VSC7427-02 12.4 Pins by Name for VSC7427-02 13 Package Information 13.1 Package Drawing 13.2 Thermal Specifications 13.3 Moisture Sensitivity 14 Design Guidelines 14.1 Power Supplies 14.2 Power Supply Decoupling 14.3 Reference Clock 14.3.1 Single-Ended RefClk Input 14.4 Interfaces 14.4.1 General Recommendations 14.4.2 SGMII Interface 14.4.3 Parallel Interface 14.4.4 Serial Interface 14.4.5 Enhanced SerDes Interface 14.4.6 Two-Wire Serial Interface 14.4.7 DDR2 SDRAM Interface 14.4.8 Thermal Diode External Connection 15 Design Considerations 15.1 10BASE-T mode unable to re-establish link 15.2 Software script for link performance 15.3 10BASE-T signal amplitude 15.4 Clause 45 register 7.60 15.5 Clause 45 register 3.22 15.6 Clause 45 register 3.1 15.7 Clause 45 register address post-increment 15.8 IEEE1588 Out of Sync Situation 15.8.1 Copper Port (internal CuPHY 10-11 and External PHYs Without Timestamping) 15.8.2 Serdes Port (SFP) 16 Ordering Information