Datasheet LAN9303, LAN9303i (Microchip)

LAN9303/LAN9303i Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII PRODUCT FEATURES Data Brief Highlights
„ Switch Management — Port mirroring/monitoring/sniffing: ingress and/or egress „ Up to 200Mbps via Turbo MII Interface traffic on any port or port pair — Fully compliant statistics (MIB) gathering counters „ High performance, full featured 3 port switch with VLAN, QoS packet prioritization, Rate Limiting, IGMP — Control registers configurable on-the-fly monitoring and management functions „ Ports — Port 0 - MII MAC, MII PHY, RMII PHY modes „ Serial management via I2C or SMI — 2 internal 10/100 PHYs with HP Auto-MDIX support „ Unique Virtual PHY feature simplifies software — 200Mbps Turbo MII (PHY or MAC mode) development by mimicking the multiple switch ports — Fully compliant with IEEE 802.3 standards as a single port PHY — 10BASE-T and 100BASE-TX support — Full and half duplex support
Target Applications
— Full duplex flow control — Backpressure (forced collision) half duplex flow control — Automatic flow control based on programmable levels „ Cable, satellite, and IP set-top boxes — Automatic 32-bit CRC generation and checking „ Digital televisions — 2K Jumbo packet support „ Digital video recorders — Programmable interframe gap, flow control pause value „ VoIP/Video phone systems — Full transmit/receive statistics — Full LED support per port „ Home gateways — Auto-negotiation „ Test/Measurement equipment — Automatic polarity correction „ Industrial automation systems — Automatic MDI/MDI-X — Loop-back mode
Key Benefits
„ Serial Management — I2C (slave) access to all internal registers „ Ethernet Switch Fabric — MIIM (MDIO) access to PHY related registers — 32K buffer RAM — SMI (extended MIIM) access to all internal registers — 512 entry forwarding table „ Other Features — Port based IEEE 802.1Q VLAN support (16 groups) — General Purpose Timer – Programmable IEEE 802.1Q tag insertion/removal — I2C Serial EEPROM interface — IEEE 802.1D spanning tree protocol support — Programmable GPIOs/LEDs — 4 separate transmit queues available per port — Fixed or weighted egress priority servicing „ Single 3.3V power supply — QoS/CoS Packet prioritization „ 56-pin QFN (8x8 mm) Lead-Free RoHS Compliant – Input priority determined by VLAN tag, DA lookup, Package TOS, DIFFSERV or port default value „ Available in Commercial & Industrial Temp. Ranges – Programmable Traffic Class map based on input priority on per port basis – Remapping of 802.1Q priority field on per port basis – Programmable rate limiting at the ingress with coloring and random early discard, per port / priority – Programmable rate limiting at the egress with leaky bucket algorithm, per port / priority — IGMP v1/v2/v3 monitoring for Multicast packet filtering — Programmable broadcast storm protection with global % control and enable per port — Programmable buffer usage limits — Dynamic queues on internal memory — Programmable filter by MAC address SMSC LAN9303/LAN9303i
PRODUCT PREVIEW
Revision 1.5 (07-08-11) Document Outline General Description Block Diagram Figure 1 Internal Block Diagram Package Outline 56-QFN Package Outline Figure 2 56-QFN Package Definition Table 1 56-QFN Dimensions Figure 3 56-QFN Recommended PCB Land Pattern