Datasheet KSZ8895MLUB (Microchip) - 5

KSZ8895MLUB 1.0 INTRODUCTION 1.1 General Description
The KSZ8895MLUB is a highly integrated Layer 2-managed 5-port switch with an optimized design and plentiful fea- tures, qualified to meet AEC-Q100 standard for automotive applications. It is designed for cost-sensitive 10/100 Mbps 5-port switch systems with on-chip termination, lowest power consumption, and internal core power controller. These features will save more system cost. It has 1.4 Gbps high-performance memory bandwidth, shared memory based switch fabric with full non-blocking configuration. It also provides an extensive feature set such as power management, programmable rate limit and priority ratio, tag/port-based VLAN, packets filtering, quality-of-service (QoS) four-queue prioritization, management interface, and MIB counters. Port 5 is a MAC 5 MII interface with PHY mode as default at switch side. The SW5-MII interface can be connected to a processor with a MAC MII interface. The KSZ8895MLUB consists of 10/100 PHYs with patented and enhanced mixed-signal technology, media access con- trol (MAC) units, a high-speed non-blocking switch fabric, a dedicated address lookup engine, and an on-chip frame buffer memory. The KSZ8895MLUB contains five MACs and four integrated PHYs. All PHYs support 10/100BASE-T/ TX. All registers of MACs and PHYs units can be managed by the SPI interface or the SMI interface. MIIM registers of the PHYs can be accessed through the MDC/MDIO interface. EEPROM can set all control registers for the unmanaged mode. The KSZ8895MLUB provides multiple CPU control/data interfaces to effectively address both current and emerging fast Ethernet applications.
FIGURE 1-1: FUNCTIONAL DIAGRAM KSZ8895MLUB
10/100 10/100 AUTO MDI/MDIX T/Tx 1 FIFO, FLOW CONTROL, VLAN 1K LOOK-UP MAC 1 PHY1 ENGINE 10/100 10/100 AUTO MDI/MDIX T/Tx 2 MAC 2 PHY2 QUEUE MANAGEMENT 10/100 10/100 AUTO MDI/MDIX T/Tx 3 MAC 3 PHY3 10/100 BUFFER 10/100 AUTO MDI/MDIX T/Tx 4 MANAGEMENT MAC 4 PHY4 SW5-MII 10/100 T FRAME MAC 5 AGGING, PRIORITY BUFFERS MDC, MDI/O FOR MIIM AND SMI SNI SNI MIB CONTROL REG SPI I/F SPI COUNTERS LED0[5:1] LED1[5:1] LED I CONTROL EEPROM LED2[5:1] REGISTERS I/F  2018 Microchip Technology Inc. DS00002680A-page 5 Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Physical Layer Transceiver 3.2 Power 3.3 Power Management 3.4 Switch Core 3.5 Advanced Functionality 3.6 MII Management (MIIM) Interface 3.7 Serial Management Interface (SMI) 4.0 Register Descriptions 4.1 Global Registers 4.2 Port Registers 4.3 Advanced Control Registers 4.4 Static MAC Address Table 4.5 VLAN Table 4.6 Dynamic MAC Address Table 4.7 Management Information Base (MIB) Counters 4.8 MIIM Registers 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings*** 6.0 Electrical Characteristics 7.0 Timing Diagrams 7.1 EEPROM Timing 7.2 SNI Timing 7.3 MII Timing 7.4 SPI Timing 7.5 Auto-Negotiation Timing 7.6 Reset Timing 8.0 Reset Circuit 9.0 Selection of Isolation Transformer, (Note 9-1) 10.0 Package Outline Appendix A: Data Sheet Revision History The Microchip Web Site Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service