Datasheet KSZ8893FQL (Microchip) - 10
| Fabricante | Microchip |
| Descripción | Single-Chip 3-Port Switch with Fiber Support |
| Páginas / Página | 109 / 10 — KSZ8893FQL. TABLE 2-1:. SIGNALS (CONTINUED). Type. Pin. Note. … |
| Formato / tamaño de archivo | PDF / 2.2 Mb |
| Idioma del documento | Inglés |
KSZ8893FQL. TABLE 2-1:. SIGNALS (CONTINUED). Type. Pin. Note. Description. Number. Name. 2-1
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KSZ8893FQL TABLE 2-1: SIGNALS (CONTINUED) Type Pin Pin Note Description Number Name 2-1
In MC loopback mode, 1 = Drop OAM frames and Ethernet frames with the following errors – CRS, undersize, oversize. Loopback Ethernet frames with only good CRC and valid 18 P1LCRCD IPD length. 0 = Drop OAM frames only. Loopback all Ethernet frames including those with errors. 1 = Perform MC loopback at PHY of port 1. 19 P1LPBM IPD 0 = Perform MC loopback at MAC of port 2 Port 2 LED indicator Note: An external 1 kΩ pull-down is needed on this pin if it is connected to an 20 P2LED3 OPD LED. The 1 kΩ resistor will not turn ON the LED. See description in pin 4. 21 DGND GND Digital ground. 1.2V digital VDD Provides V VDDC/ OUT_1V2 to KSZ8893FQL’s input power pins: VDDAP (pin 63), 22 P VDDC (pins 91 and 123), and VDDA (pins 38, 43, and 57). It is recommended VOUT_1V2 the pin should be connected to 3.3V power rail by a 100Ω resistor for the internal LDO application. LED display mode select. 23 LEDSEL1 IPD See description in pins 1 and 4. 24 NC O No connect Port 1 LED indicator Note: An external 1 kΩ pull-down is needed on this pin if it is connected to an 25 P1LED3 OPD LED. The 1 kΩ resistor will not turn ON the LED. See description in pin 1. Strap pin for RMII Mode 1 = Enable 26 RMII_EN OPD 0 = Disable After reset, this pin has no meaning and is a no connect. Hardware pin overwrite 1 = Enable: All strap-in pin configurations are overwritten by the EEPROM configuration data, except for P2ANEN (pin 13), P2SPD (pin 14), P2DPX (pin 27 HWPOVR IPD 15) and ML_EN (pin 34). After reset, the pin state for P2ANEN, P2SPD and P2DPX is polled by the KSZ8893FQL. 0 = Disable: All strap-in pin configurations are overwritten by the EEPROM configuration data. Port 2 Auto MDI/MDI-X 28 P2MDIXDIS IPD PD (default) = enable PU = disable Port 2 MDI/MDI-X setting when auto MDI/MDI-X is disabled. 29 P2MDIX IPD PD (default) = MDI-X (transmit on TXP2/TXM2 pins) PU = MDI, (transmit on RXP2/RXM2 pins) 1 = Enable auto-negotiation on port 1 30 P1ANEN IPU 0 = Disable auto-negotiation on port 1 DS00003038B-page 10 2019 Microchip Technology Inc. Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Media Conversion 3.2 Physical Layer Transceiver 3.3 MAC and Switch 3.4 Advanced Switch Functions 3.5 Unicast MAC Address Filtering 3.6 Configuration Interface 3.7 Loopback Support 4.0 Register Descriptions 4.1 MII Management (MIIM) Registers 4.2 Register Descriptions 4.3 Register Map: Switch, PHY, TS-1000 Media Converter (8-bit registers) 4.4 Register Descriptions 4.5 Advanced Control Registers (Registers 96-141) 4.6 Static MAC Address Table 4.7 VLAN Table 4.8 Dynamic MAC Address Table 4.9 Management Information Base (MIB) Counters 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Specifications 7.1 EEPROM Timing 7.2 SNI Timing 7.3 MII Timing 7.4 RMII Timing 7.5 SPI Timing 7.6 Auto-Negotiation Timing 7.7 Reset Timing 8.0 Reset Circuit 9.0 Selection of Isolation Transformers 10.0 Package Outline 10.1 Package Marking Information Appendix A: Data Sheet Revision History The Microchip Web Site Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service
In MC loopback mode, 1 = Drop OAM frames and Ethernet frames with the following errors – CRS, undersize, oversize. Loopback Ethernet frames with only good CRC and valid 18 P1LCRCD IPD length. 0 = Drop OAM frames only. Loopback all Ethernet frames including those with errors. 1 = Perform MC loopback at PHY of port 1. 19 P1LPBM IPD 0 = Perform MC loopback at MAC of port 2 Port 2 LED indicator Note: An external 1 kΩ pull-down is needed on this pin if it is connected to an 20 P2LED3 OPD LED. The 1 kΩ resistor will not turn ON the LED. See description in pin 4. 21 DGND GND Digital ground. 1.2V digital VDD Provides V VDDC/ OUT_1V2 to KSZ8893FQL’s input power pins: VDDAP (pin 63), 22 P VDDC (pins 91 and 123), and VDDA (pins 38, 43, and 57). It is recommended VOUT_1V2 the pin should be connected to 3.3V power rail by a 100Ω resistor for the internal LDO application. LED display mode select. 23 LEDSEL1 IPD See description in pins 1 and 4. 24 NC O No connect Port 1 LED indicator Note: An external 1 kΩ pull-down is needed on this pin if it is connected to an 25 P1LED3 OPD LED. The 1 kΩ resistor will not turn ON the LED. See description in pin 1. Strap pin for RMII Mode 1 = Enable 26 RMII_EN OPD 0 = Disable After reset, this pin has no meaning and is a no connect. Hardware pin overwrite 1 = Enable: All strap-in pin configurations are overwritten by the EEPROM configuration data, except for P2ANEN (pin 13), P2SPD (pin 14), P2DPX (pin 27 HWPOVR IPD 15) and ML_EN (pin 34). After reset, the pin state for P2ANEN, P2SPD and P2DPX is polled by the KSZ8893FQL. 0 = Disable: All strap-in pin configurations are overwritten by the EEPROM configuration data. Port 2 Auto MDI/MDI-X 28 P2MDIXDIS IPD PD (default) = enable PU = disable Port 2 MDI/MDI-X setting when auto MDI/MDI-X is disabled. 29 P2MDIX IPD PD (default) = MDI-X (transmit on TXP2/TXM2 pins) PU = MDI, (transmit on RXP2/RXM2 pins) 1 = Enable auto-negotiation on port 1 30 P1ANEN IPU 0 = Disable auto-negotiation on port 1 DS00003038B-page 10 2019 Microchip Technology Inc. Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Media Conversion 3.2 Physical Layer Transceiver 3.3 MAC and Switch 3.4 Advanced Switch Functions 3.5 Unicast MAC Address Filtering 3.6 Configuration Interface 3.7 Loopback Support 4.0 Register Descriptions 4.1 MII Management (MIIM) Registers 4.2 Register Descriptions 4.3 Register Map: Switch, PHY, TS-1000 Media Converter (8-bit registers) 4.4 Register Descriptions 4.5 Advanced Control Registers (Registers 96-141) 4.6 Static MAC Address Table 4.7 VLAN Table 4.8 Dynamic MAC Address Table 4.9 Management Information Base (MIB) Counters 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Specifications 7.1 EEPROM Timing 7.2 SNI Timing 7.3 MII Timing 7.4 RMII Timing 7.5 SPI Timing 7.6 Auto-Negotiation Timing 7.7 Reset Timing 8.0 Reset Circuit 9.0 Selection of Isolation Transformers 10.0 Package Outline 10.1 Package Marking Information Appendix A: Data Sheet Revision History The Microchip Web Site Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service