Datasheet 5P35021 (IDT) - 10

5P35021 Datasheet
Table 10. PD# Priority PD# I2C_OE_EN_bit SE1, DIFF1/DIFF2, SEx_PPS Output Notes
0 x x Stop 32kHz free run 1 0 x Stop 1 1 0 Stop 1 1 1 Running
Reference Input and Selection
When programming, the 5P35021 accepts 8MHz–40MHz crystal input, 8MHz to 125MHz differential clocks input or 1MHz–125MHz LVCMOS (to X1) input. See below reference circuit for details.
Crystal Input (X1/X2)
The crystal oscillators should be fundamental mode quartz crystals; overtone crystals are not suitable. Crystal frequency should be specified for parallel resonance with 40MHz maximum. A crystal manufacturer wil calibrate its crystals to the nominal frequency with a certain load capacitance value. When the oscillator load capacitance matches the crystal load capacitance, the oscillation frequency wil be accurate as 0 PPM. When the oscil ator load capacitance is lower than the crystal load capacitance, the oscillation frequency wil be higher than nominal. In order to get an accurate oscillation frequency, the matching the oscillator load capacitance with the crystal load capacitance is required. To set the oscil ator load capacitance, 5P35021 has built-in two programmable tuning capacitors inside the chip, one at XIN and one at XOUT. They can be adjusted independently. The value of each capacitor is composed of a fixed capacitance amount plus a variable capacitance amount set with the XTAL[7:0] register. Adjustment of the crystal tuning capacitors allows for maximum flexibility to accommodate crystals from various manufacturers. The range of tuning capacitor values available are in accordance with the following table. ©2019 Integrated Device Technology, Inc. 10 October 4, 2019 Document Outline Description Typical Applications Key Specifications Features Output Features Block Diagram Pin Assignments Figure 1. Pin Assignments for 3 x 3 mm 20-VFQFPN Package – Top View Pin Descriptions Table 1. Pin Descriptions Power Group Table 2. Power Group Output Sources Table 3. Output Source Table 4. Output Source Selection Register Settings Table 5. DIFF1 Output Table 6. DIFF2 Output Device Features and Functions DFC – Dynamic Frequency Control Figure 2. DFC Function Block Diagram Table 7. DFC Function Priority DFC Function Programming PPS – Proactive Power Saving Function Figure 3. PPS Function Block Diagram Figure 4. PPS Assertion/Deassertion Timing Chart PPS Function Programming Timer Function Description Figure 5. Timer Functions OE Pin Function Table 8. OE Pin Functions Table 9. OE Pin Function Summary Table 10. PD# Priority Reference Input and Selection Crystal Input (X1/X2) Table 11. Programmable Tuning Caps Spread Spectrum Analog Spread Spectrum Digital Spread Spectrum Figure 6. Digital Spread Spectrum VBAT Table 12. VBAT Switching Threshold ORT–VCO Overshoot Reduction Technology PLL Features and Descriptions Table 13. Output 1 Divider Table 14. Output 2, 4, and 5 Divider Table 15. Output 3 Divider Output Clock Test Conditions Figure 7. LVCMOS Output Test Conditions Figure 8. LP-HCSL Output Test Conditions Absolute Maximum Ratings Table 16. Absolute Maximum Ratings Recommended Operating Conditions Table 17. Recommended Operating Conditions Electrical Characteristics Table 18. Input Capacitance, LVCMOS Output Impedance, and Internal Pull-down Resistance Table 19. Crystal Characteristics Table 20. DC Electrical Characteristics (Industrial)1,2 Table 21. DC Electrical Characteristics (Automotive)1,2 Table 22. Input Parameters1,2 Table 23. Power Consumption of 32.768kHz Output Only Operation Table 24. DC Electrical Characteristics – 3.3V LVCMOS Table 25. DC Electrical Characteristics – 2.5V LVCMOS Table 26. DC Electrical Characteristics – 1.8V LVCMOS Table 27. Electrical Characteristics – DIF 0.7V LPHCSL Differential Outputs Table 28. Electrical Characteristics – LVDS Table 29. Electrical Characteristics – LVPECL Figure 9. Output Differential Voltage Swing AC Electrical Characteristics Table 30. AC Electrical Characteristics PCI Express Jitter Specifications Table 31. PCI Express Jitter Specifications Spread Spectrum Generation Specifications Table 32. Spread Spectrum Generation Specifications I2C Bus Characteristics Table 33. I2C Bus DC Characteristics Table 34. I2C Bus AC Characteristics I2C Mode Operations Figure 10. I2C Slave Read and Write Cycle Sequencing Glossary of Features Table 35. Glossary of Features Package Outline Drawings Marking Diagrams (industrial) Marking Diagrams (automotive) Ordering Information Revision History