Datasheet 5P35021 (IDT) - 8

link to page 9 5P35021 Datasheet
Figure 4. PPS Assertion/Deassertion Timing Chart PPS Function Programming
▪ Refer to the OE Pin Functions table to have the proper PPS function selected for OE pin(s). Note that the register default is set to Output enable (OE) function for OE pins. ▪ Have proper setup to Byte 30 and 32 for OE1–OE3 function selection; for PPS function, select 10 to control register bits.
Timer Function Description
1. The timer function can be used together with the DFC -Dynamic Frequency Control function or with another PLL frequency programming. 2. The timer provides 4 different delay times by two bits selection: 0.5 sec – 1 sec – 2 sec – 4 sec. 3. The timeout flag will be set when timer times out and the flag can be cleared by writing 0 to timer enable bit. 4. When timer times out, RESET pin can generate a 250ms pulse signal if RESET control bit is enabled. 5. When timer times out, DFC stage will switch back to DFC00 setting if DFC function is enabled, and DFC function will be disabled after RESET. ©2019 Integrated Device Technology, Inc. 8 October 4, 2019 Document Outline Description Typical Applications Key Specifications Features Output Features Block Diagram Pin Assignments Figure 1. Pin Assignments for 3 x 3 mm 20-VFQFPN Package – Top View Pin Descriptions Table 1. Pin Descriptions Power Group Table 2. Power Group Output Sources Table 3. Output Source Table 4. Output Source Selection Register Settings Table 5. DIFF1 Output Table 6. DIFF2 Output Device Features and Functions DFC – Dynamic Frequency Control Figure 2. DFC Function Block Diagram Table 7. DFC Function Priority DFC Function Programming PPS – Proactive Power Saving Function Figure 3. PPS Function Block Diagram Figure 4. PPS Assertion/Deassertion Timing Chart PPS Function Programming Timer Function Description Figure 5. Timer Functions OE Pin Function Table 8. OE Pin Functions Table 9. OE Pin Function Summary Table 10. PD# Priority Reference Input and Selection Crystal Input (X1/X2) Table 11. Programmable Tuning Caps Spread Spectrum Analog Spread Spectrum Digital Spread Spectrum Figure 6. Digital Spread Spectrum VBAT Table 12. VBAT Switching Threshold ORT–VCO Overshoot Reduction Technology PLL Features and Descriptions Table 13. Output 1 Divider Table 14. Output 2, 4, and 5 Divider Table 15. Output 3 Divider Output Clock Test Conditions Figure 7. LVCMOS Output Test Conditions Figure 8. LP-HCSL Output Test Conditions Absolute Maximum Ratings Table 16. Absolute Maximum Ratings Recommended Operating Conditions Table 17. Recommended Operating Conditions Electrical Characteristics Table 18. Input Capacitance, LVCMOS Output Impedance, and Internal Pull-down Resistance Table 19. Crystal Characteristics Table 20. DC Electrical Characteristics (Industrial)1,2 Table 21. DC Electrical Characteristics (Automotive)1,2 Table 22. Input Parameters1,2 Table 23. Power Consumption of 32.768kHz Output Only Operation Table 24. DC Electrical Characteristics – 3.3V LVCMOS Table 25. DC Electrical Characteristics – 2.5V LVCMOS Table 26. DC Electrical Characteristics – 1.8V LVCMOS Table 27. Electrical Characteristics – DIF 0.7V LPHCSL Differential Outputs Table 28. Electrical Characteristics – LVDS Table 29. Electrical Characteristics – LVPECL Figure 9. Output Differential Voltage Swing AC Electrical Characteristics Table 30. AC Electrical Characteristics PCI Express Jitter Specifications Table 31. PCI Express Jitter Specifications Spread Spectrum Generation Specifications Table 32. Spread Spectrum Generation Specifications I2C Bus Characteristics Table 33. I2C Bus DC Characteristics Table 34. I2C Bus AC Characteristics I2C Mode Operations Figure 10. I2C Slave Read and Write Cycle Sequencing Glossary of Features Table 35. Glossary of Features Package Outline Drawings Marking Diagrams (industrial) Marking Diagrams (automotive) Ordering Information Revision History