Datasheet AD8565, AD8566, AD8567 (Analog Devices) - 9

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Data Sheet AD8565/AD8566/AD8567 THEORY OF OPERATION
The AD8565/AD8566/AD8567 are designed to drive large The benefit of this type of input stage is low bias current. The capacitive loads in LCD applications. They have high output input bias current is the sum of base currents of Q4 to Q5 and current drive and rail-to-rail input/output operation and are Q6 to Q8 over the range from (VNEG + 1 V) to (VPOS − 1 V). powered from a single 16 V supply. They are also intended for Outside this range, the input bias current is dominated by the other applications where low distortion and high output current sum of base currents of Q10 to Q11 for input signals close to drive are needed. VNEG and of Q6 to Q8 (Q10 to Q11) for signals close to VPOS. Figure 28 shows a simplified equivalent circuit for the AD8565/ From this type of design, the input bias current of the AD8565/ AD8566/AD8567. The rail-to-rail bipolar input stage is com- AD8566/AD8567 not only exhibits different amplitude but also posed of two PNP differential pairs, Q4 to Q5 and Q10 to Q11, exhibits different polarities. Figure 29 provides the characteris- operating in series with diode protection networks, D1 to D2. tics of the input bias current vs. the common-mode voltage. It is Diode network D1 to D2 serves as protection against large important to keep in mind that the source impedances driving transients for Q4 to Q5 to accommodate rail-to-rail input swing. the inputs are balanced for optimum dc and ac performance. D5 to D6 protect Q10 to Q11 against Zenering. In normal oper-
1000 V
ation, Q10 to Q11 are off, and their input stage is buffered from
S = 16V 800 TA = 25°C
the operational amplifier inputs by Q6 to D3 and Q8 to D4.
600 A)
Operation of the input stage is best understood as a function of
n ( 400
applied common-mode voltage: when the inputs of the AD8565/
NT 200
AD8566/AD8567 are biased midway between the supplies, the
0
differential signal path gain is controlled by resistive loads Q4 to
CURRE AS –200
Q5 (via R9, R10). As the input common-mode level is reduced
BI
toward the negative supply (V
UT –400
NEG or GND), the input transistor
INP
current sources, I1 and I2, are forced into saturation, thereby
–600
forcing the Q6 to D3 and Q8 to D4 networks into cutoff.
–800
However, Q4 to Q5 remain active, providing input stage gain.
–1000 0 2 4 6 8 10 12 14 16
029 Inversely, when common-mode input voltage is increased
INPUT COMMON-MODE VOLTAGE (V)
01909- toward the positive supply, Q4 to Q5 are driven into cutoff, Q3 Figure 29. AD8565/AD8566/AD8567 Input Bias Current vs. is driven into saturation, and Q4 becomes active, providing bias Common-Mode Voltage to the Q10 to Q11 differential pair. The point at which the Q10 to To achieve rail-to-rail output performance, the AD8565/ Q11 differential pair becomes active is approximately equal to AD8566/AD8567 design uses a complementary common- (VPOS − 1 V). source (or gmRL) output. This configuration allows output
V
voltages to approach the power supply rails, particularly if the
POS
output transistors are allowed to enter the triode region on extremes of signal swing, which are limited by V
R1
GS, the transistor sizes, and output load current. In addition, this type
BIAS LINE Q3 Q4
of output stage exhibits voltage gain in an open-loop gain configuration. The amount of gain depends on the total load
D1 D2
resistance at the output of the AD8565/AD8566/AD8567.
R3 R4 INPUT OVERVOLTAGE PROTECTION Q6 Q8 C1 V+ Q4 Q5 V–
As with any semiconductor device, whenever the input exceeds either supply voltages, attention needs to be paid to the input
D3 R5 R6 D4
overvoltage characteristics. As an overvoltage occurs, the amplifier
C2
could be damaged, depending on the voltage level and the
Q10 Q11
magnitude of the fault current. When the input voltage exceeds
D5
either supply by more than 0.6 V, internal positive-negative (pn) junctions allow current to flow from the input to the supplies.
I1 D6 I2 FOLDED CASCADE R9 R10
028
VNEG
01909- Figure 28. AD8565/AD8566/AD8567 Equivalent Input Circuit Rev. H | Page 9 of 13 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION PIN CONFIGURATIONS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION INPUT OVERVOLTAGE PROTECTION OUTPUT PHASE REVERSAL POWER DISSIPATION THERMAL PAD—AD8567 TOTAL HARMONIC DISTORTION + NOISE (THD + N) SHORT-CIRCUIT OUTPUT CONDITIONS LCD PANEL APPLICATIONS OUTLINE DIMENSIONS ORDERING GUIDE