Datasheet LTC2050, LTC2050HV (Analog Devices) - 10

LTC2050/LTC2050HV
APPLICATIONS INFORMATION Shutdown
output multiplied by the closed loop gain of the op amp. To reduce this form of clock feedthrough, use smaller The LTC2050 includes a shutdown pin in the 6-lead valued gain setting resistors and minimize the source SOT-23 and the SO-8 version. When this active low pin resistance at the input. If the resistance seen at the inputs is high or allowed to float, the device operates normally. is less than 10k, this form of clock feedthrough is less When the shutdown pin is pulled low, the device enters than 1µVRMS input referred at 7.5kHz, or less than the shutdown mode; supply current drops to 3µA, all clock- amount of residue clock feedthrough from the first form ing stops, and both inputs and output assume a high described above. impedance state. Placing a capacitor across the feedback resistor reduces
Clock Feedthrough, Input Bias Current
either form of clock feedthrough by limiting the bandwidth of the closed loop gain. The LTC2050 uses auto-zeroing circuitry to achieve an almost zero DC offset over temperature, common mode Input bias current is defined as the DC current into the voltage, and power supply voltage. The frequency of the input pins of the op amp. The same current spikes that clock used for auto-zeroing is typically 7.5kHz. The term cause the second form of clock feedthrough described clock feedthrough is broadly used to indicate visibility of above, when averaged, dominate the DC input bias current this clock frequency in the op amp output spectrum. There of the op amp below 70°C. are typically two types of clock feedthrough in auto zeroed At temperatures above 70°C, the leakage of the ESD pro- op amps like the LTC2050. tection diodes on the inputs increases the input bias cur- The first form of clock feedthrough is caused by the settling rents of both inputs in the positive direction, while the of the internal sampling capacitor and is input referred; current caused by the charge injection stays relatively that is, it is multiplied by the closed loop gain of the op constant. At elevated temperatures (above 85°C) the amp. This form of clock feedthrough is independent of the leakage current begins to dominate and both the negative magnitude of the input source resistance or the magni- and positive pin’s input bias currents are in the positive tude of the gain setting resistors. The LTC2050 has a resi- direction (into the pins). due clock feedthrough of less then 1µVRMS input referred at 7.5kHz.
Input Pins, ESD Sensitivity
The second form of clock feedthrough is caused by the ESD voltages above 700V on the input pins of the op amp small amount of charge injection occurring during the will cause the input bias currents to increase (more DC sampling and holding of the op amp’s input offset volt- current into the pins). At these voltages, it is possible to age. The current spikes are multiplied by the impedance damage the device to a point where the input bias current seen at the input terminals of the op amp, appearing at the exceeds the maximums specified in this data sheet. Rev. F 10 For more information www.analog.com Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Test Circuits Applications Information Typical Applications Package Description Revision History Typical Application Related Parts