Preliminary Datasheet EPC2152 (Efficient Power Conversion) - 5

EPC2152 – 80 V, 12.5 A ePower™ Stage PRELIMINARY Electrical Characteristics
All ratings are specified at TA = 25˚C. Nominal VIN = 48 V, VDD = 12 V, (VBOOT – VSW) = 12 V unless otherwise indicated.
Symbol Parameter Test Conditions Min Typ Max Units Operating Power Supply
IDDQ Off State Total Quiescent Current HSin & LSin = OFF, VDD=12V 22 mA IDD_1MHz Total Operating Current @1MHz PWM=1MHz, 50% On-Time 29 mA IDD_3MHz Total Operating Current @3MHz PWM=3MHz, 50% On-Time 42 mA
Bootstrap Power Supply
IBOOTQ Off State Bootstrap Supply Current HSin = OFF, (VBOOT – VSW) = 12V 8 mA IBOOT_1MHz Bootstrap Supply Current @1MHz HS PWM=1MHz, 50% On-Time 13 mA IBOOT_3MHz Bootstrap Supply Current @3MHz HS PWM=3MHz, 50% On-Time 20 mA VSYNC_BOOT Sync Boot Generated (VBOOT -VSW) ISYNC_BOOT = 20mA 11.5 V
Undervoltage Lockout
VDD (UVLO+) UVLO Trip Level VDD Rising LSin = ON, VDD Ramps Up 7.50 V VDD (HYST) UVLO VDD Fal ing Hysteresis LSin = ON, VDD Ramps Down 0.75 V VBOOT (UVLO+) UVLO Trip Level (VBOOT -VSW) Rising HSin = ON, VBOOT Ramps Up 7.25 V VBOOT (HYST) UVLO (VBOOT-VSW) Fal ing Hysteresis HSin = ON, VBOOT Ramps Down 0.75 V
Logic Input Pins
VIH High-level Logic Threshold HSin, LSin Rising 2.4 V VIL Low-level Logic Threshold HSin, LSin Fal ing 0.8 V VIHyst Logic Threshold Hysteresis VIH Rising – VIL Fal ing 0.5 V Rin Input Pul down Resistance HSin, LSin = 5V 5 kΩ
Output Power FETs
RDS(on)_HS High Side FET RDS(on) IDS = +/-10A, HSin=ON, LSin=OFF 8.5 mΩ VHS_DS_Clamp High Side 3rd Quadrant Clamp IDS = -10A, HSin & LSin = OFF -2 V RDS(on)_LS Low Side FET RDS(on) IDS = +/-10A, LSin=ON, HSin=OFF 8.5 mΩ VLS_DS_Clamp Low Side 3rd Quadrant Clamp IDS = -10A, HSin & LSin = OFF -2 V ILEAK_VIN-SW Leakage Current VIN to SW HSin = OFF, VIN = 80V, SW = 0V 100 µA ILEAK_SW-GND Leakage Current SW to GND LSin = OFF, SW = 80V 100 µA
Dynamic Characteristics (Logic Input to Output Switching Node)
(see Figure 1. Timing Diagram and Test Circuit) t_delayHS_on High-Side On Propagation Delay SW = 0V and HS FET Turn-On 20 ns t_delayLS_on Low-Side On Propagation Delay SW = 60V and LS FET Turn-On 20 ns t_delayHS_off High-Side Off Propagation Delay SW = 60V and HS FET Turn-Off 20 ns t_delayLS_off Low-Side Off Proprgation Delay SW = 0V and LS FET Turn-Off 20 ns t_matchon Delay Matching LSoff to HSon LS Turn-Off to HS Turn-On 0 ns t_matchOff Delay Matching HSoff to LSon HS Turn-Off to LS Turn-On 0 ns PW_min Minimum Input Pulse-Width 50% to 50% Width 20 ns Subject to Change without Notice www.epc-co.com COPYRIGHT 2020 Rev 1.1 Page 5